4 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c
index b169775456bb..563a87efd593 100644
--- a/src/mainboard/asus/m4a785-m/get_bus_conf.c
+++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -107,7 +107,7 @@ void get_bus_conf(void)
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index d152f71d7dcb..3b681434c0b1 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -197,7 +197,7 @@ static void m4a785m_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 4a276fb0c3c8..d7951cf8beea 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
 #else
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 870af70f654b..f0be2f77930c 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();