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-rw-r--r--src/mainboard/google/brya/variants/agah/overridetree.cb9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb
index ad23f7b6f1dc..70bc09289d42 100644
--- a/src/mainboard/google/brya/variants/agah/overridetree.cb
+++ b/src/mainboard/google/brya/variants/agah/overridetree.cb
@@ -58,6 +58,15 @@ chip soc/intel/alderlake
}"
device domain 0 on
+ device ref pcie4_0 on
+ # Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_req = 0,
+ .clk_src = 0,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ device pci 00.0 alias dgpu on end
+ end
device ref dtt on
chip drivers/intel/dptf
## sensor information