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-rw-r--r--src/mainboard/google/hatch/Kconfig2
-rw-r--r--src/mainboard/google/hatch/dsdt.asl2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 749b0df30afb..712ed06e7ccc 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -166,7 +166,7 @@ config CHROMEOS
select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU
config CHROMEOS_WIFI_SAR
- bool "Enable SAR options for Chrome OS build"
+ bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS
select DSAR_ENABLE
select GEO_SAR_ENABLE
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 022a607a1df8..dad2267c338a 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -35,7 +35,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */