diff options
Diffstat (limited to 'src/mainboard/google/ninja/chromeos.c')
-rw-r--r-- | src/mainboard/google/ninja/chromeos.c | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/src/mainboard/google/ninja/chromeos.c b/src/mainboard/google/ninja/chromeos.c deleted file mode 100644 index fa4c66f98f7e..000000000000 --- a/src/mainboard/google/ninja/chromeos.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> - -/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ -#define WP_STATUS_PAD 36 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {ssus_get_gpio(WP_STATUS_PAD), ACTIVE_HIGH, 0, "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. The - * hardware defaults to an input but there is a 20K pulldown. Externally - * there is a 10K pullup. Disable the internal pull in romstage so that - * there isn't any ambiguity in the reading. - */ -#if defined(__PRE_RAM__) - ssus_disable_internal_pull(WP_STATUS_PAD); -#endif - - /* WP is enabled when the pin is reading high. */ - return ssus_get_gpio(WP_STATUS_PAD); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(0x2008, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} |