diff options
Diffstat (limited to 'src/mainboard/google')
11 files changed, 14 insertions, 55 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2631b616cebf..bca948e9d52c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -107,17 +107,6 @@ chip soc/intel/jasperlake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # PCIE Root Port Configuration - register "PcieRpEnable[0]" = "0" - register "PcieRpEnable[1]" = "0" - register "PcieRpEnable[2]" = "0" - register "PcieRpEnable[3]" = "0" - register "PcieRpEnable[4]" = "0" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - # PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN. - register "PcieRpEnable[7]" = "1" - register "PcieClkSrcUsage[0]" = "0xff" register "PcieClkSrcUsage[1]" = "0xff" register "PcieClkSrcUsage[2]" = "0xff" @@ -394,7 +383,7 @@ chip soc/intel/jasperlake device pci 1c.5 off end # PCI Express Root Port 6 device pci 1c.6 off end # PCI Express Root Port 7 # External PCIe port 4 is mapped to PCIe Root port 8 - device pci 1c.7 on end # PCI Express Root Port 8 - WLAN + device pci 1c.7 on end # PCI Express Root Port 8 - hosts M.2 E-key WLAN device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 device pci 1e.2 on diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c index e14e95650d77..d43d08f8561c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/ramstage.c +++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c @@ -6,6 +6,7 @@ #include <drivers/usb/acpi/chip.h> #include <fw_config.h> #include <gpio.h> +#include <soc/pci_devs.h> #include <ec/google/chromeec/ec.h> #include <device/pci_ops.h> #include <intelblocks/power_limit.h> diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index ab6fc16408c1..36eadcbd1f2a 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -46,19 +46,14 @@ chip soc/intel/jasperlake .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index e7f2562fc922..6a2093845fa0 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -8,8 +8,6 @@ chip soc/intel/jasperlake register "SlowSlewRate" = "SlewRateFastBy8" register "FastPkgCRampDisable" = "1" - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" diff --git a/src/mainboard/google/dedede/variants/dexi/overridetree.cb b/src/mainboard/google/dedede/variants/dexi/overridetree.cb index 2b09088eef10..f53a11a89e43 100644 --- a/src/mainboard/google/dedede/variants/dexi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dexi/overridetree.cb @@ -38,19 +38,14 @@ chip soc/intel/jasperlake .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index 5bc127dc5882..c7d6afb495a7 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -38,19 +38,14 @@ chip soc/intel/jasperlake .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/dedede/variants/dita/overridetree.cb b/src/mainboard/google/dedede/variants/dita/overridetree.cb index 2b09088eef10..f53a11a89e43 100644 --- a/src/mainboard/google/dedede/variants/dita/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dita/overridetree.cb @@ -38,19 +38,14 @@ chip soc/intel/jasperlake .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index ce816e581bfd..dcd5cbb83de9 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/jasperlake - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 5e4de2ac2a64..1b1df26db1aa 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -8,8 +8,6 @@ fw_config end chip soc/intel/jasperlake - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" @@ -227,6 +225,7 @@ chip soc/intel/jasperlake end end end #I2C 4 + device pci 1c.7 off end # PCI Express Root Port 8 device pci 1f.3 on chip drivers/generic/alc1015 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 1aa2e711a975..cfaf28fbfa3e 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -7,8 +7,6 @@ fw_config end chip soc/intel/jasperlake - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" @@ -381,5 +379,6 @@ chip soc/intel/jasperlake device i2c 28 on end end end # I2C 5 + device pci 1c.7 off end # PCI Express Root Port 8 end end diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb index 2b09088eef10..f53a11a89e43 100644 --- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb +++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb @@ -38,19 +38,14 @@ chip soc/intel/jasperlake .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" |