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-rw-r--r--src/mainboard/hp/z220_series/acpi/pci.asl35
-rw-r--r--src/mainboard/hp/z220_series/dsdt.asl1
2 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/hp/z220_series/acpi/pci.asl b/src/mainboard/hp/z220_series/acpi/pci.asl
new file mode 100644
index 000000000000..6277ac6f4e10
--- /dev/null
+++ b/src/mainboard/hp/z220_series/acpi/pci.asl
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Intel PCI to PCI bridge 0:1e.0
+
+Device (PCIB)
+{
+ Name (_ADR, 0x001e0000) // _ADR: Address
+ Name (_PRW, Package() { 13, 4 }) // Power Resources for Wake
+
+ Method (_PRT) // _PRT: PCI Interrupt Routing Table
+ {
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 0x14 },
+ Package() { 0x0000ffff, 1, 0, 0x15 },
+ Package() { 0x0000ffff, 2, 0, 0x16 },
+ Package() { 0x0000ffff, 3, 0, 0x17 },
+ Package() { 0x0001ffff, 0, 0, 0x15 },
+ Package() { 0x0001ffff, 1, 0, 0x16 },
+ Package() { 0x0001ffff, 2, 0, 0x17 },
+ Package() { 0x0001ffff, 3, 0, 0x14 },
+ })
+ }
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/hp/z220_series/dsdt.asl b/src/mainboard/hp/z220_series/dsdt.asl
index af4f3eacf996..57149b75b1bf 100644
--- a/src/mainboard/hp/z220_series/dsdt.asl
+++ b/src/mainboard/hp/z220_series/dsdt.asl
@@ -23,6 +23,7 @@ DefinitionBlock(
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include "acpi/pci.asl"
}
}
}