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-rw-r--r--src/mainboard/protectli/vault_cml/devicetree.cb248
1 files changed, 248 insertions, 0 deletions
diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb
new file mode 100644
index 000000000000..154d81a4a9e9
--- /dev/null
+++ b/src/mainboard/protectli/vault_cml/devicetree.cb
@@ -0,0 +1,248 @@
+chip soc/intel/cannonlake
+ # Enable Enhanced Intel SpeedStep
+ register "eist_enable" = "1"
+
+ register "cpu_pl2_4_cfg" = "baseline"
+
+ register "gen1_dec" = "0x00fc0201"
+ register "gen2_dec" = "0x007c0a01"
+ register "gen3_dec" = "0x000c03e1"
+ register "gen4_dec" = "0x001c02e1"
+
+ # GPIO
+ register "PchUnlockGpioPads" = "1"
+ register "gpe0_dw0" = "0x2"
+ register "gpe0_dw1" = "0x3"
+ register "gpe0_dw2" = "0xd"
+
+ # FSP configuration
+ register "SaGv" = "SaGv_Enabled"
+ register "ScsEmmcHs400Enabled" = "1"
+
+ # Enable eDP device
+ register "DdiPortEdp" = "1" # Display Port
+
+ # Enable HPD for DDI ports B/C
+ register "DdiPortBHpd" = "1" # HDMI
+ register "DdiPortCHpd" = "1" # USB Type-C
+
+ # Enable DDC for DDI port B
+ register "DdiPortBDdc" = "1" # HDMI
+
+ register "PchHdaAudioLinkHda" = "1"
+
+ # Misc
+ register "AcousticNoiseMitigation" = "1"
+
+ # Power
+ register "PchPmSlpS3MinAssert" = "3" # 50ms
+ register "PchPmSlpS4MinAssert" = "1" # 1s
+ register "PchPmSlpSusMinAssert" = "2" # 500ms
+ register "PchPmSlpAMinAssert" = "4" # 2s
+
+ register "tcc_offset" = "20" # TCC of 80C
+
+ # Enable SERIRQ continuous
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "SkipExtGfxScan" = "1"
+
+ register "enable_c6dram" = "1"
+
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[2]" = "1"
+
+ register "PcieRpEnable[4]" = "1" # LAN1
+ register "PcieRpEnable[5]" = "1" # LAN2
+ register "PcieRpEnable[6]" = "1" # LAN3
+ register "PcieRpEnable[7]" = "1" # LAN4
+ register "PcieRpEnable[8]" = "1" # LAN5
+ register "PcieRpEnable[9]" = "1" # LAN6
+ register "PcieRpEnable[11]" = "1" # M.2 WiFi
+ register "PcieRpEnable[12]" = "1" # M.2 NVMe x4
+
+ # Enable Advanced Error Reporting for RP 5-10, 12, 13
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpAdvancedErrorReporting[5]" = "1"
+ register "PcieRpAdvancedErrorReporting[6]" = "1"
+ register "PcieRpAdvancedErrorReporting[7]" = "1"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpAdvancedErrorReporting[9]" = "1"
+ register "PcieRpAdvancedErrorReporting[11]" = "1"
+ register "PcieRpAdvancedErrorReporting[12]" = "1"
+
+ # Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13
+ register "PcieRpLtrEnable[4]" = "1"
+ register "PcieRpLtrEnable[5]" = "1"
+ register "PcieRpLtrEnable[6]" = "1"
+ register "PcieRpLtrEnable[7]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpLtrEnable[9]" = "1"
+ register "PcieRpLtrEnable[11]" = "1"
+ register "PcieRpLtrEnable[12]" = "1"
+
+ register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
+ register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
+
+ # USB related
+ register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+ USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(4) | \
+ USB_PORT_WAKE_ENABLE(5) | \
+ USB_PORT_WAKE_ENABLE(6) | \
+ USB_PORT_WAKE_ENABLE(7) | \
+ USB_PORT_WAKE_ENABLE(8) | \
+ USB_PORT_WAKE_ENABLE(9)"
+
+ register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+ USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(4)"
+
+ register "PchUsb2PhySusPgDisable" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M2 WiFi
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # 4G/LTE
+ register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[4]" = "USB3_PORT_EMPTY"
+ register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+ [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART0] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ device cpu_cluster 0 on end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on end # SA Thermal device
+ device pci 08.0 off end # Gaussian Mixture Model
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.5 off end # SDCard
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 on end # eMMC
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 on end # PCI Express Port 5 LAN1
+ device pci 1c.5 on end # PCI Express Port 6 LAN2
+ device pci 1c.6 on end # PCI Express Port 7 LAN3
+ device pci 1c.7 on end # PCI Express Port 8 LAN4
+ device pci 1d.0 on end # PCI Express Port 9 LAN5
+ device pci 1d.1 on end # PCI Express Port 10 LAN6
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 on end # PCI Express Port 12 M.2 WiFi
+ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
+ "M.2/E 2230 (M2_WIFI2)" "SlotDataBusWidth1X"
+ device pci 1d.4 on # PCI Express Port 13 NVMe
+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+ "M.2/M 2280 (J1)" "SlotDataBusWidth4X"
+ end
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on
+ chip superio/ite/it8786e
+ register "TMPIN1.mode" = "THERMAL_PECI"
+ register "TMPIN1.offset" = "0x63"
+ register "TMPIN2.mode" = "THERMAL_MODE_DISABLED"
+ register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
+ register "ec.vin_mask" = "VIN_ALL"
+ register "ec.smbus_24mhz" = "1"
+ register "ec.smbus_en" = "1"
+ # FAN1 is CPU fan (connector on board)
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = " 1"
+ register "FAN1.smart.tmp_off" = "40"
+ register "FAN1.smart.tmp_start" = "60"
+ register "FAN1.smart.tmp_full" = "85"
+ register "FAN1.smart.tmp_delta" = " 2"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "24"
+ register "FAN2.mode" = "FAN_MODE_OFF"
+ register "FAN3.mode" = "FAN_MODE_OFF"
+ device pnp 2e.1 on # COM 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # COM 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off end # Printer Port
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0xa40
+ io 0x62 = 0xa30
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.8 off end # COM 3
+ device pnp 2e.9 off end # COM 4
+ device pnp 2e.a off end # CIR
+ device pnp 2e.b off end # COM 5
+ device pnp 2e.c off end # COM 6
+ end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 hidden end # P2SB
+ device pci 1f.2 hidden end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-07 05:29:39 +0000