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Diffstat (limited to 'src/mainboard/tyan/s2850/romstage.c')
| -rw-r--r-- | src/mainboard/tyan/s2850/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index e990f4ecf3ab..567b4f1ec455 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -89,7 +89,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); #endif |