diff options
Diffstat (limited to 'src/mainboard/tyan/s2880')
| -rw-r--r-- | src/mainboard/tyan/s2880/devicetree.cb | 12 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2880/irq_tables.c | 4 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2880/mptable.c | 22 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2880/romstage.c | 6 |
4 files changed, 22 insertions, 22 deletions
diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb index 122648e13774..97dcae866af7 100644 --- a/src/mainboard/tyan/s2880/devicetree.cb +++ b/src/mainboard/tyan/s2880/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory @@ -66,7 +66,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -84,15 +84,15 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2880/irq_tables.c b/src/mainboard/tyan/s2880/irq_tables.c index 78c12016b44e..19149df14210 100644 --- a/src/mainboard/tyan/s2880/irq_tables.c +++ b/src/mainboard/tyan/s2880/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -37,5 +37,5 @@ const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr); + return copy_pirq_routing_table(addr); } diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index a8f3859d7bee..94a150b0319c 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -29,7 +29,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -89,14 +89,14 @@ static void *smp_write_config_table(void *v) printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); bus_chain_0 = 1; } - + /* 8111 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } + bus_isa++; + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -134,14 +134,14 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); @@ -165,7 +165,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); @@ -205,7 +205,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);// -//Slot 4 PCIX 100/66 +//Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 7c0e4f2a2c1a..f75c541b9c85 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); |