diff options
Diffstat (limited to 'src/mainboard/via/epia-m/Config.lb')
| -rw-r--r-- | src/mainboard/via/epia-m/Config.lb | 159 |
1 files changed, 0 insertions, 159 deletions
diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb deleted file mode 100644 index 011ce5ad2427..000000000000 --- a/src/mainboard/via/epia-m/Config.lb +++ /dev/null @@ -1,159 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -object vgabios.o - -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - object acpi_tables.o -end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/via/vt8623 - - device apic_cluster 0 on - chip cpu/via/model_c3 - device apic 0 on end - end - end - - device pci_domain 0 on - chip southbridge/via/vt8235 - - device pci 10.0 on end # USB 1.1 - device pci 10.1 on end # USB 1.1 - device pci 10.2 on end # USB 1.1 - device pci 10.3 on end # USB 2 - - device pci 11.0 on # Southbridge - chip superio/via/vt1211 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - - end - end - - device pci 11.1 on end # IDE - # 2-4 non existant? - device pci 11.5 on end # AC97 Audio - device pci 11.6 off end # AC97 Modem - device pci 12.0 on end # Ethernet - end -# This is on the EPIA MII, not the M. - chip southbridge/ricoh/rl5c476 - register "enable_cf" = "1" - device pci 0a.0 on end - device pci 0a.1 on end - end - end -end |