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-rw-r--r--src/mainboard/apple/macbook21/romstage.c26
-rw-r--r--src/mainboard/asrock/g41c-gs/romstage.c7
-rw-r--r--src/mainboard/asus/p5gc-mx/romstage.c26
-rw-r--r--src/mainboard/asus/p5qpl-am/romstage.c6
-rw-r--r--src/mainboard/foxconn/g41s-k/romstage.c3
-rw-r--r--src/mainboard/getac/p470/romstage.c26
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c26
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/romstage.c11
-rw-r--r--src/mainboard/ibase/mb899/romstage.c26
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c26
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c6
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c26
-rw-r--r--src/mainboard/lenovo/t60/romstage.c26
-rw-r--r--src/mainboard/lenovo/thinkcentre_a58/romstage.c6
-rw-r--r--src/mainboard/lenovo/x60/romstage.c26
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c26
16 files changed, 17 insertions, 282 deletions
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 32a7871ecf1c..89db57e392a2 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -195,31 +195,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 6);
- RCBA32(GCS) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- /* next step only on ich7m b0 and later: */
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 0228499181b1..bb7a342d75c7 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -36,7 +36,6 @@
static void mb_lpc_setup(void)
{
- u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -65,11 +64,7 @@ static void mb_lpc_setup(void)
RCBA8(OIC) = 0x03;
RCBA8(OIC);
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 5);
- RCBA32(GCS) = reg32;
-
- RCBA32(CG) = 0x00000001;
+ ich7_setup_cir();
}
static void ich7_enable_lpc(void)
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 632ef05573e1..20a2b56c513c 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -145,31 +145,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030509;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 6);
- RCBA32(GCS) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index dc589a591892..30480ad3d5d6 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -131,7 +131,6 @@ static int setup_sio_gpio(void)
static void mb_lpc_setup(void)
{
- u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -142,10 +141,7 @@ static void mb_lpc_setup(void)
RCBA8(0x31ff) = 0x03;
RCBA8(0x31ff);
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 5);
- RCBA32(GCS) = reg32;
- RCBA32(CG) = 0x00000001;
+ ich7_setup_cir();
}
static void ich7_enable_lpc(void)
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index a22c90c1f1d8..0bfbbfe28ce0 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -67,7 +67,8 @@ static void mb_lpc_setup(void)
RCBA8(OIC);
RCBA32(FD) |= FD_INTLAN;
- RCBA32(CG) = 0x00000001;
+
+ ich7_setup_cir();
}
static void ich7_enable_lpc(void)
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index a7c64bd98b94..0b7aea49f4d5 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -204,31 +204,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(0x3410);
- reg32 |= (1 << 6);
- RCBA32(0x3410) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index eaf05a2c386d..65750cfd6cdb 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -107,31 +107,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030509;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 6);
- RCBA32(GCS) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 989a0cb9417c..d4ce9401c12b 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -96,16 +96,7 @@ static void mb_gpio_init(void)
RCBA8(OIC) = 0x03;
RCBA8(OIC);
- RCBA32(GCS) = 0x00190464;
- RCBA32(CG) = 0x00000000;
- RCBA32(0x3430) = 0x00000001;
- RCBA32(0x3e00) = 0xff000001;
- RCBA32(0x3e08) = 0x00000080;
- RCBA32(0x3e0c) = 0x00800000;
- RCBA32(0x3e40) = 0xff000001;
- RCBA32(0x3e48) = 0x00000080;
- RCBA32(0x3e4c) = 0x00800000;
- RCBA32(0x3f00) = 0x0000000b;
+ ich7_setup_cir();
}
static void ich7_enable_lpc(void)
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 82dbba5dc522..1c3202f710fd 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -169,31 +169,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 6);
- RCBA32(GCS) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index bad2b6d5388a..f6fc8df2f43f 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -89,31 +89,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(0x3410);
- reg32 |= (1 << 6);
- RCBA32(0x3410) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 74f86221eb0b..81d50670e9ba 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -32,7 +32,6 @@
static void mb_lpc_setup(void)
{
- u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -55,10 +54,7 @@ static void mb_lpc_setup(void)
RCBA8(0x31ff) = 0x03;
RCBA8(0x31ff);
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 5);
- RCBA32(GCS) = reg32;
- RCBA32(CG) = 0x00000001;
+ ich7_setup_cir();
}
static void ich7_enable_lpc(void)
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 7fa1b4271eeb..9995760e1f77 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -212,31 +212,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 6);
- RCBA32(GCS) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- /* next step only on ich7m b0 and later: */
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 9e832208b533..1fe16a98c614 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -129,31 +129,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 6);
- RCBA32(GCS) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index e4abab5770c5..cb84ce07f517 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -30,7 +30,6 @@
static void mb_lpc_setup(void)
{
- u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -41,10 +40,7 @@ static void mb_lpc_setup(void)
RCBA8(0x31ff) = 0x03;
RCBA8(0x31ff);
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 5);
- RCBA32(GCS) = reg32;
- RCBA32(CG) = 0x00000001;
+ ich7_setup_cir();
}
static void ich7_enable_lpc(void)
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 5a8ab942bcc5..8189f8a39657 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -129,31 +129,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 6);
- RCBA32(GCS) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index f550632d30a6..57d9c4afffd6 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -168,31 +168,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 6);
- RCBA32(GCS) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- /* next step only on ich7m b0 and later: */
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
static void init_artec_dongle(void)
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-21 22:33:27 +0000