diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/chausie/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/chausie/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/skyrim/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/skyrim/variants/skyrim/overridetree.cb | 4 |
5 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig index 477620ca471e..e9fd743fbbfd 100644 --- a/src/mainboard/amd/chausie/Kconfig +++ b/src/mainboard/amd/chausie/Kconfig @@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select EC_ACPI - select SOC_AMD_SABRINA + select SOC_AMD_MENDOCINO select SOC_AMD_COMMON_BLOCK_USE_ESPI select AMD_SOC_CONSOLE_UART select MAINBOARD_HAS_CHROMEOS @@ -74,7 +74,7 @@ config RO_REGION_ONLY string depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A # Add the EFS and EC to the RO region only - # This is a chausie-specific override of soc/amd/sabrina/Kconfig + # This is a chausie-specific override of soc/amd/mendocino/Kconfig default "apu/amdfw apu/ecfw" config CHROMEOS diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index c0806a5c0746..5cfd42f0f10f 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -chip soc/amd/sabrina +chip soc/amd/mendocino register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, .generic_io_range[0] = { diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index f00775824fe1..e96940df038e 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 select PSP_DISABLE_POSTCODES # TODO re-enable PSP postcodes later (b/227199049) - select SOC_AMD_SABRINA + select SOC_AMD_MENDOCINO select SOC_AMD_COMMON_BLOCK_USE_ESPI select TPM_GOOGLE_TI50 diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 71f1a5f510c5..9d4b12ceb000 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -chip soc/amd/sabrina +chip soc/amd/mendocino # eSPI Configuration register "common_config.espi_config" = "{ @@ -213,4 +213,4 @@ chip soc/amd/sabrina device generic 3 on end end -end # chip soc/amd/sabrina +end # chip soc/amd/mendocino diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 89cc63cb0f92..d8dc59bd459a 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -26,7 +26,7 @@ fw_config end end -chip soc/amd/sabrina +chip soc/amd/mendocino device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller @@ -241,4 +241,4 @@ chip soc/amd/sabrina end end # UART1 -end # chip soc/amd/sabrina +end # chip soc/amd/mendocino |