diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/ocp/deltalake/Kconfig | 32 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/Kconfig.name | 2 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/Makefile.inc | 11 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/acpi/platform.asl | 365 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/board.fmd | 11 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/board_info.txt | 5 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/bootblock.c | 62 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/devicetree.cb | 80 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/dsdt.asl | 23 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/fadt.c | 9 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/ramstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/romstage.c | 24 |
12 files changed, 631 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig new file mode 100644 index 000000000000..679115a5bdf8 --- /dev/null +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -0,0 +1,32 @@ +if BOARD_OCP_DELTALAKE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select FSP_CAR + select HAVE_ACPI_TABLES + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_COOPERLAKE_SP + select SUPERIO_ASPEED_AST2400 + +config MAINBOARD_DIR + string + default "ocp/deltalake" + +config MAINBOARD_PART_NUMBER + string + default "DeltaLake" + +config MAINBOARD_FAMILY + string + default "DeltaLake" + +config MAX_SOCKET + int + default 1 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif # BOARD_OCP_DELTALAKE diff --git a/src/mainboard/ocp/deltalake/Kconfig.name b/src/mainboard/ocp/deltalake/Kconfig.name new file mode 100644 index 000000000000..c59421fc3685 --- /dev/null +++ b/src/mainboard/ocp/deltalake/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_DELTALAKE + bool "DeltaLake" diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc new file mode 100644 index 000000000000..bfdd78ed8828 --- /dev/null +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c + +CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ +CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/deltalake/acpi/platform.asl b/src/mainboard/ocp/deltalake/acpi/platform.asl new file mode 100644 index 000000000000..e04bde5d191f --- /dev/null +++ b/src/mainboard/ocp/deltalake/acpi/platform.asl @@ -0,0 +1,365 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +Name (_S0, Package () // mandatory system state +{ + 0x00, 0x00, 0x00, 0x00 +}) + +Name (_S5, Package () // mandatory system state +{ + 0x07, 0x00, 0x00, 0x00 +}) + +/* The APM port can be used for generating software SMIs */ +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} + +/* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 /* IO-Trap at 0x808 */ +} + +OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400) +Field (PSYS, ByteAcc, NoLock, Preserve) +{ + PLAT, 32, // Platform ID + + // IOAPIC + APC0, 1, // PCH IOAPIC Enable + AP00, 1, // PC00 IOAPIC Enable + AP01, 1, // PC01 IOAPIC Enable + AP02, 1, // PC02 IOAPIC Enable + AP03, 1, // PC03 IOAPIC Enable + AP04, 1, // PC04 IOAPIC Enable + AP05, 1, // PC05 IOAPIC Enable + AP06, 1, // PC06 IOAPIC Enable + AP07, 1, // PC07 IOAPIC Enable + AP08, 1, // PC08 IOAPIC Enable + AP09, 1, // PC09 IOAPIC Enable + AP10, 1, // PC10 IOAPIC Enable + AP11, 1, // PC11 IOAPIC Enable + AP12, 1, // PC12 IOAPIC Enable + AP13, 1, // PC13 IOAPIC Enable + AP14, 1, // PC14 IOAPIC Enable + AP15, 1, // PC15 IOAPIC Enable + AP16, 1, // PC16 IOAPIC Enable + AP17, 1, // PC17 IOAPIC Enable + AP18, 1, // PC18 IOAPIC Enable + AP19, 1, // PC19 IOAPIC Enable + AP20, 1, // PC20 IOAPIC Enable + AP21, 1, // PC21 IOAPIC Enable + AP22, 1, // PC22 IOAPIC Enable + AP23, 1, // PC23 IOAPIC Enable + RESA, 7, + SKOV, 1, // Override Socket APIC Id + RES0, 7, + + // Power Management + TPME, 1, + CSEN, 1, + C3EN, 1, + C6EN, 1, + C7EN, 1, + MWOS, 1, + PSEN, 1, + EMCA, 1, + HWAL, 2, + KPRS, 1, + MPRS, 1, + TSEN, 1, + FGTS, 1, + OSCX, 1, + RESX, 1, + + // RAS + CPHP, 8, + IIOP, 8, + IIOH, 64, + PRBM, 32, + P0ID, 32, + P1ID, 32, + P2ID, 32, + P3ID, 32, + P4ID, 32, + P5ID, 32, + P6ID, 32, + P7ID, 32, + P0BM, 64, + P1BM, 64, + P2BM, 64, + P3BM, 64, + P4BM, 64, + P5BM, 64, + P6BM, 64, + P7BM, 64, + MEBM, 16, + MEBC, 16, + CFMM, 32, + TSSY, 32, // TODO: This is TSSZ in system booted from production FW + M0BS, 64, + M1BS, 64, + M2BS, 64, + M3BS, 64, + M4BS, 64, + M5BS, 64, + M6BS, 64, + M7BS, 64, + M0RN, 64, + M1RN, 64, + M2RN, 64, + M3RN, 64, + M4RN, 64, + M5RN, 64, + M6RN, 64, + M7RN, 64, + SMI0, 32, + SMI1, 32, + SMI2, 32, + SMI3, 32, + SCI0, 32, + SCI1, 32, + SCI2, 32, + SCI3, 32, + MADD, 64, + CUU0, 128, + CUU1, 128, + CUU2, 128, + CUU3, 128, + CUU4, 128, + CUU5, 128, + CUU6, 128, + CUU7, 128, + CPSP, 8, + ME00, 128, + ME01, 128, + ME10, 128, + ME11, 128, + ME20, 128, + ME21, 128, + ME30, 128, + ME31, 128, + ME40, 128, + ME41, 128, + ME50, 128, + ME51, 128, + ME60, 128, + ME61, 128, + ME70, 128, + ME71, 128, + MESP, 16, + LDIR, 64, + PRID, 32, + AHPE, 8, + + // VTD + DHRD, 192, + ATSR, 192, + RHSA, 192, + + // SR-IOV + WSIC, 8, + WSIS, 16, + WSIB, 8, + WSID, 8, + WSIF, 8, + WSTS, 8, + WHEA, 8, + + // BIOS Guard + BGMA, 64, + BGMS, 8, + BGIO, 16, + BGIL, 8, + CNBS, 8, + + // USB3 + XHMD, 8, + SBV1, 8, + SBV2, 8, + + // HWPM + HWEN, 2, + ACEN, 1, + HWPI, 1, + RES1, 4, + + // IIO + BB00, 8, + BB01, 8, + BB02, 8, + BB03, 8, + BB04, 8, + BB05, 8, + BB06, 8, + BB07, 8, + BB08, 8, + BB09, 8, + BB10, 8, + BB11, 8, + BB12, 8, + BB13, 8, + BB14, 8, + BB15, 8, + BB16, 8, + BB17, 8, + BB18, 8, + BB19, 8, + BB20, 8, + BB21, 8, + BB22, 8, + BB23, 8, + BB24, 8, + BB25, 8, + BB26, 8, + BB27, 8, + BB28, 8, + BB29, 8, + BB30, 8, + BB31, 8, + BB32, 8, + BB33, 8, + BB34, 8, + BB35, 8, + BB36, 8, + BB37, 8, + BB38, 8, + BB39, 8, + BB40, 8, + BB41, 8, + BB42, 8, + BB43, 8, + BB44, 8, + BB45, 8, + BB46, 8, + BB47, 8, + SGEN, 8, + SG00, 8, + SG01, 8, + SG02, 8, + SG03, 8, + SG04, 8, + SG05, 8, + SG06, 8, + SG07, 8, + + // Performance + CLOD, 8, + + // XTU + XTUB, 32, + XTUS, 32, + XMBA, 32, + DDRF, 8, + RT3S, 8, + RTP0, 8, + RTP3, 8, + + // FPGA + FBB0, 8, + FBB1, 8, + FBB2, 8, + FBB3, 8, + FBB4, 8, + FBB5, 8, + FBB6, 8, + FBB7, 8, + FBL0, 8, + FBL1, 8, + FBL2, 8, + FBL3, 8, + FBL4, 8, + FBL5, 8, + FBL6, 8, + FBL7, 8, + P0FB, 8, + P1FB, 8, + P2FB, 8, + P3FB, 8, + P4FB, 8, + P5FB, 8, + P6FB, 8, + P7FB, 8, + FMB0, 32, + FMB1, 32, + FMB2, 32, + FMB3, 32, + FMB4, 32, + FMB5, 32, + FMB6, 32, + FMB7, 32, + FML0, 32, + FML1, 32, + FML2, 32, + FML3, 32, + FML4, 32, + FML5, 32, + FML6, 32, + FML7, 32, + FKPB, 32, + FKB0, 8, + FKB1, 8, + FKB2, 8, + FKB3, 8, + FKB4, 8, + FKB5, 8, + FKB6, 8, + FKB7, 8 +} + +/* SMI I/O Trap */ +Method (TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/ocp/deltalake/board.fmd b/src/mainboard/ocp/deltalake/board.fmd new file mode 100644 index 000000000000..24c7f33876c8 --- /dev/null +++ b/src/mainboard/ocp/deltalake/board.fmd @@ -0,0 +1,11 @@ +FLASH 64M { + SI_ALL@0x0 0x3000000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2FE7000 + PLATFORM_DATA@0x2FE8000 0x10000 + } + SI_BIOS@0x3000000 0x1000000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x800 0xfff800 + } +} diff --git a/src/mainboard/ocp/deltalake/board_info.txt b/src/mainboard/ocp/deltalake/board_info.txt new file mode 100644 index 000000000000..f5c07009db5e --- /dev/null +++ b/src/mainboard/ocp/deltalake/board_info.txt @@ -0,0 +1,5 @@ +Board name: DeltaLake +Category: server +ROM protocol: SPI +ROM socketed: yes +Release year: 2020 diff --git a/src/mainboard/ocp/deltalake/bootblock.c b/src/mainboard/ocp/deltalake/bootblock.c new file mode 100644 index 000000000000..8004170a5ee5 --- /dev/null +++ b/src/mainboard/ocp/deltalake/bootblock.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE); + uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN); + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); + pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, + com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb new file mode 100644 index 000000000000..26912d113d21 --- /dev/null +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -0,0 +1,80 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/cpx + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # configure device interrupt routing + register "ir00_routing" = "0x3210" # IR00, Dev31 + register "ir01_routing" = "0x3210" # IR01, Dev30 + register "ir02_routing" = "0x3210" # IR02, Dev29 + register "ir03_routing" = "0x3210" # IR03, Dev28 + register "ir04_routing" = "0x3210" # IR04, Dev27 + + # configure interrupt polarity control + register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow + register "ipc1" = "0x00000000" # IPC1 + register "ipc2" = "0x00000000" # IPC2 + register "ipc3" = "0x00000000" # IPC3 + + # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs + # FB production turbo_ratio_limit is 0x1f1f1f2022222325 + register "turbo_ratio_limit" = "0x1b1b1b1d20222325" + # FB production turbo_ratio_limit_cores is 0x1c1812100c080402 + register "turbo_ratio_limit_cores" = "0x1c1814100c080402" + + # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL + register "pstate_req_ratio" = "0xa" + + register "coherency_support" = "0" + register "ats_support" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end # Intel SkyLake-E CBDMA Registers + device pci 04.1 on end # Intel SkyLake-E CBDMA Registers + device pci 04.2 on end # Intel SkyLake-E CBDMA Registers + device pci 04.3 on end # Intel SkyLake-E CBDMA Registers + device pci 04.4 on end # Intel SkyLake-E CBDMA Registers + device pci 04.5 on end # Intel SkyLake-E CBDMA Registers + device pci 04.6 on end # Intel SkyLake-E CBDMA Registers + device pci 04.7 on end # Intel SkyLake-E CBDMA Registers + device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers + device pci 05.2 on end # Intel SkyLake-E RAS + device pci 05.4 on end # Intel SkyLake-E IOAPIC + device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers + device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers + device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers + device pci 11.0 on end # Intel Device a26c: PCU + + # PCH devices + device pci 11.5 on end # Intel C620 Series Chipset Family SSATA Controller [AHCI mode] + device pci 14.0 on end # Intel C620 Series Chipset Family USB 3.0 xHCI Controller + + device pci 14.2 on end # Signal processing controller: Intel Device a231 + device pci 16.0 on end # Communication controller: Intel Device a23a + device pci 16.1 on end # Communication controller: Intel Device a23b + device pci 16.4 on end # Communication controller: Intel Device a23e + device pci 1c.0 on end # PCI bridge: Intel Device a210 + device pci 1c.4 on end # PCI bridge: Intel Device a214 + device pci 1c.5 on end # PCI bridge: Intel Device a215 + device pci 1d.0 on end # PCI bridge: Intel Device a218 + device pci 1f.0 on end # ISA bridge: Intel Device a245 + device pci 1f.1 on end # p2sb + device pci 1f.2 on end # Memory controller: Intel Device a221 + device pci 1f.3 on end # Audio device: Intel Device a270 + device pci 1f.4 on end # Intel C620 Series Chipset Family SMBus + device pci 1f.5 on end # Intel C620 Series Chipset Family SPI Controller + end +end diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl new file mode 100644 index 000000000000..c74b5fecb881 --- /dev/null +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/xeon_sp/cpx/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + // CPX-SP ACPI tables + #include <soc/intel/xeon_sp/cpx/acpi/uncore.asl> +} diff --git a/src/mainboard/ocp/deltalake/fadt.c b/src/mainboard/ocp/deltalake/fadt.c new file mode 100644 index 000000000000..b9fcd582ef43 --- /dev/null +++ b/src/mainboard/ocp/deltalake/fadt.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <soc/acpi.h> + +void motherboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c new file mode 100644 index 000000000000..c4da6287090a --- /dev/null +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ +} diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c new file mode 100644 index 000000000000..35c7e2d14b97 --- /dev/null +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <FspmUpd.h> +#include <soc/romstage.h> + +/* +* Configure GPIO depend on platform +*/ +static void mainboard_config_gpios(FSPM_UPD *mupd) +{ + /* To be implemented */ +} + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + /* To be implemented */ +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mainboard_config_gpios(mupd); + mainboard_config_iio(mupd); +} |