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-rw-r--r--src/northbridge/intel/sch/sch.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h
index 3eb082585d82..9ac79ea8d14e 100644
--- a/src/northbridge/intel/sch/sch.h
+++ b/src/northbridge/intel/sch/sch.h
@@ -36,7 +36,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
#define DEFAULT_GPE0BASE 0x5C0
#define DEFAULT_SMMCNTRLBASE 0x3F703F76
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */