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-rw-r--r--src/soc/amd/cezanne/romstage.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 57c19615d975..573b353c798e 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -4,6 +4,7 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h>
+#include <amdblocks/pmlib.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <fsp/api.h>
@@ -20,6 +21,9 @@ asmlinkage void car_stage_entry(void)
post_code(0x41);
+ /* Snapshot chipset state prior to any FSP call */
+ fill_chipset_state();
+
fsp_memory_init(acpi_is_wakeup_s3());
soc_update_apob_cache();