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Diffstat (limited to 'src/soc/intel/skylake/chip.c')
-rw-r--r--src/soc/intel/skylake/chip.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 5c1cc6113f83..7c77a8966cf7 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -34,18 +34,18 @@
#include "chip.h"
static const struct pcie_rp_group pch_lp_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group pch_h_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
/* Sunrise Point PCH-H actually only has 4 ports in the
third group. But that would require a runtime check
and probing 4 non-existent ports shouldn't hurt. */
- { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 },
{ 0 }
};