diff options
Diffstat (limited to 'src/soc/intel/skylake/pch.c')
| -rw-r--r-- | src/soc/intel/skylake/pch.c | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c index 7084fa28a40e..451bebb083d7 100644 --- a/src/soc/intel/skylake/pch.c +++ b/src/soc/intel/skylake/pch.c @@ -16,14 +16,10 @@ */ #include <arch/io.h> -#include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <soc/pch.h> #include <soc/pci_devs.h> -#include <soc/ramstage.h> u8 pch_revision(void) { @@ -34,33 +30,3 @@ u16 pch_type(void) { return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); } - -#if ENV_RAMSTAGE -void pch_enable_dev(device_t dev) -{ - /* FSP should implement routines to disable PCH IPs */ - u32 reg32; - - /* These devices need special enable/disable handling */ - switch (PCI_SLOT(dev->path.pci.devfn)) { - case PCH_DEV_SLOT_PCIE: - return; - } - - if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); - - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - } else { - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } -} - -#endif |