diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/northbridge.asl | 7 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/dtt/Kconfig | 9 | ||||
| -rw-r--r-- | src/soc/intel/common/block/dtt/dtt.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/acpi/gpio.asl | 69 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/gpio.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h | 19 |
9 files changed, 105 insertions, 18 deletions
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index a304331f1d3f..fcbd1d0494b2 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -124,5 +124,12 @@ Device (PDRC) /* PCI Device Resource Consumption */ } } +/* Get PCIe BAR */ +Method (GPCB, 0, Serialized) +{ + Local0 = \_SB.PCI0.MCHC.PXBR << 28 + Return (Local0) +} + /* GFX 00:02.0 */ #include <drivers/intel/gma/acpi/gfx.asl> diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index c01f36fdace7..591abbeaaed4 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -220,8 +220,6 @@ struct soc_intel_cannonlake_config { /* Gfx related */ bool SkipExtGfxScan; - bool Device4Enable; - /* CPU PL2/4 Config * Performance: Maximum PLs for maximum performance. * Baseline: Baseline PLs for balanced performance at lower power. diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 55a7c92aa080..993efbb10785 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -631,7 +631,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * the `Heci1Disabled` UPD to `0`. */ s_cfg->Heci1Disabled = 0; - s_cfg->Device4Enable = config->Device4Enable; + s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_TS); /* Teton Glacier hybrid storage support */ s_cfg->TetonGlacierMode = config->TetonGlacierMode; diff --git a/src/soc/intel/common/block/dtt/Kconfig b/src/soc/intel/common/block/dtt/Kconfig index 1735c2ac21eb..fcf67888326d 100644 --- a/src/soc/intel/common/block/dtt/Kconfig +++ b/src/soc/intel/common/block/dtt/Kconfig @@ -7,3 +7,12 @@ config SOC_INTEL_COMMON_BLOCK_DTT Minimal PCI Driver for enabling SSDT generation of Intel Dynamic Tuning Technology (DTT) policies and controls, also known as Intel DPTF (Dynamic Platform and Thermal Framework) + +config SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL + bool + depends on SOC_INTEL_COMMON_BLOCK_DTT + default n + help + Mainboards which include `soc/intel/common/acpi/dptf/dptf.asl` + should select this to avoid generating a duplicate TCPU ACPI + device and rendering the SSDT invalid. diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index b2ce8b9c41e8..1d0451fc787f 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -21,8 +21,8 @@ static const unsigned short pci_device_ids[] = { static void dtt_acpi_fill_ssdt(const struct device *dev) { - /* Skip if DPTF driver in use since TCPU device will already exist */ - if (CONFIG(DRIVERS_INTEL_DPTF)) + /* Skip if DPTF driver or common DPTF ASL in use since TCPU device will already exist */ + if (CONFIG(DRIVERS_INTEL_DPTF) || CONFIG(SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL)) return; const char *scope = acpi_device_scope(dev); diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index b1bff143a909..beda98acbe54 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -127,7 +127,7 @@ config SOC_INTEL_PANTHERLAKE_H config SOC_INTEL_WILDCATLAKE bool - select SOC_INTEL_PANTHERLAKE_U_H + select SOC_INTEL_PANTHERLAKE_BASE help Choose this option if the mainboard is built using WCL system-on-a-chip (SoC). diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl index fe73b13b78f2..18df92dd38fa 100644 --- a/src/soc/intel/pantherlake/acpi/gpio.asl +++ b/src/soc/intel/pantherlake/acpi/gpio.asl @@ -506,6 +506,28 @@ Device (GPI3) }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), +#if CONFIG(SOC_INTEL_WILDCATLAKE) + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPH + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + GPPA + }, + + Package (0x02) + { + "intc-gpio-group-2-subproperties", + VGP3 + } + } +#else Package (0x04) { Package (0x02) @@ -532,7 +554,9 @@ Device (GPI3) VGP3 } } +#endif }) +#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_PANTHERLAKE_H)) /* first bank/group in community 3: RSVD */ Name (RSVD, Package (0x02) { @@ -558,6 +582,7 @@ Device (GPI3) } } }) +#endif /* 2nd bank/group in community 3: GPP_H */ Name (GPPH, Package (0x02) { @@ -710,6 +735,22 @@ Device (GPI4) }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), +#if CONFIG(SOC_INTEL_WILDCATLAKE) + Package (0x02) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPS + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + RSVD + } + } +#else Package (0x01) { Package (0x02) @@ -718,6 +759,7 @@ Device (GPI4) GPPS } } +#endif }) /* only bank/group in community 4: GPP_S */ Name (GPPS, Package (0x02) @@ -744,6 +786,33 @@ Device (GPI4) } } }) +#if CONFIG(SOC_INTEL_WILDCATLAKE) + /* second bank/group in community 4: RSVD */ + Name (RSVD, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "RSVD" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_RSVD_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_RSVD_START_OFFSET + } + } + }) +#endif Method (_STA, 0, NotSerialized) { Return (0xF) diff --git a/src/soc/intel/pantherlake/include/soc/gpio.h b/src/soc/intel/pantherlake/include/soc/gpio.h index d7b562f17379..5f3a2e1548c9 100644 --- a/src/soc/intel/pantherlake/include/soc/gpio.h +++ b/src/soc/intel/pantherlake/include/soc/gpio.h @@ -6,12 +6,21 @@ #include <soc/gpio_defs.h> #include <intelblocks/gpio.h> +#if CONFIG(SOC_INTEL_WILDCATLAKE) +#define CROS_GPIO_NAME "INTC10EC" +#define CROS_GPIO_DEVICE0_NAME "INTC10EC:00" +#define CROS_GPIO_DEVICE1_NAME "INTC10EC:01" +#define CROS_GPIO_DEVICE2_NAME "INTC10EC:02" +#define CROS_GPIO_DEVICE3_NAME "INTC10EC:03" +#define CROS_GPIO_DEVICE4_NAME "INTC10EC:04" +#else #define CROS_GPIO_NAME "INTC10BC" #define CROS_GPIO_DEVICE0_NAME "INTC10BC:00" #define CROS_GPIO_DEVICE1_NAME "INTC10BC:01" #define CROS_GPIO_DEVICE2_NAME "INTC10BC:02" #define CROS_GPIO_DEVICE3_NAME "INTC10BC:03" #define CROS_GPIO_DEVICE4_NAME "INTC10BC:04" +#endif #define ACPI_GPIO_CID "INTC105F" #define ACPI_GPIO_HID CROS_GPIO_NAME diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h index 0ecd32a5ced1..fd44d837ce46 100644 --- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h @@ -147,7 +147,7 @@ #define COM0_GRP_PAD_START GPP_V00 #define COM0_GRP_PAD_END GPP_C23 -#define NUM_COM0_GRP_PADS (GPP_C23 - GPP_V00 + 1) +#define NUM_COM0_GRP_PADS (COM0_GRP_PAD_END - COM0_GRP_PAD_START + 1) #define NUM_COM0_GPP_PADS (NUM_GPP_V_PADS + NUM_GPP_C_PADS) #define NUM_COM0_GROUPS 2 @@ -244,7 +244,7 @@ #define COM1_GRP_PAD_START GPP_F00 #define COM1_GRP_PAD_END GPP_THC0_GSPI_CLK_LPBK -#define NUM_COM1_GRP_PADS (GPP_THC0_GSPI_CLK_LPBK - GPP_F00 + 1) +#define NUM_COM1_GRP_PADS (COM1_GRP_PAD_END - COM1_GRP_PAD_START + 1) #define NUM_COM1_GPP_PADS (NUM_GPP_F_PADS + NUM_GPP_E_PADS) #define NUM_COM1_GROUPS 2 @@ -416,17 +416,14 @@ #if CONFIG(SOC_INTEL_WILDCATLAKE) #define COM3_GRP_PAD_START GPP_H00 -#define COM3_GRP_PAD_END GPP_VGPIO3_THC3 -#define NUM_COM3_GRP_PADS (GPP_VGPIO3_THC3 - GPP_H00 + 1) -#define NUM_COM3_GPP_PADS (NUM_GPP_H_PADS + NUM_GPP_A_PADS) #define NUM_COM3_GROUPS 3 #else #define COM3_GRP_PAD_START GPP_EPD_ON -#define COM3_GRP_PAD_END GPP_VGPIO3_THC3 -#define NUM_COM3_GRP_PADS (GPP_VGPIO3_THC3 - GPP_EPD_ON + 1) -#define NUM_COM3_GPP_PADS (NUM_GPP_H_PADS + NUM_GPP_A_PADS) #define NUM_COM3_GROUPS 4 #endif +#define COM3_GRP_PAD_END GPP_VGPIO3_THC3 +#define NUM_COM3_GRP_PADS (COM3_GRP_PAD_END - COM3_GRP_PAD_START + 1) +#define NUM_COM3_GPP_PADS (NUM_GPP_H_PADS + NUM_GPP_A_PADS) /* * +----------------------------+ @@ -493,16 +490,14 @@ #if CONFIG(SOC_INTEL_WILDCATLAKE) #define COM4_GRP_PAD_END GPP_DDSP_HPDALV -#define NUM_COM4_GRP_PADS (GPP_DDSP_HPDALV - GPP_S00 + 1) #define NUM_COM4_GPP_PADS (NUM_GPP_S_PADS) #define NUM_COM4_GROUPS 2 #else #define COM4_GRP_PAD_END GPP_S07 -#define NUM_COM4_GRP_PADS (GPP_S07 - GPP_S00 + 1) #define NUM_COM4_GPP_PADS (GPP_S07 - GPP_S00 + 1) #define NUM_COM4_GROUPS 1 #endif - +#define NUM_COM4_GRP_PADS (COM4_GRP_PAD_END - COM4_GRP_PAD_START + 1) /* * +----------------------------+ * | Community 5 | @@ -631,7 +626,7 @@ #define COM5_GRP_PAD_START GPP_B00 #define COM5_GRP_PAD_END GPP_VGPIO47 -#define NUM_COM5_GRP_PADS (GPP_VGPIO47 - GPP_B00 + 1) +#define NUM_COM5_GRP_PADS (COM5_GRP_PAD_END - COM5_GRP_PAD_START + 1) #define NUM_COM5_GPP_PADS (NUM_GPP_B_PADS + NUM_GPP_D_PADS) #define NUM_COM5_GROUPS 3 |