diff options
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/common/spi.c | 5 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/spi.h | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/spi.h | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/spi.h | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/spi.h | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/spi.h | 3 |
6 files changed, 13 insertions, 8 deletions
diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index f465027ab932..8bcc56e0cb7e 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -43,8 +43,9 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, SET32_BITFIELDS(&GET_SCK_REG(regs), SPI_CFG_SCK_LOW, sck_ticks - 1, SPI_CFG_SCK_HIGH, sck_ticks - 1); - SET32_BITFIELDS(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY, tick_dly, - SPI_CFG1_CS_IDLE, cs_ticks - 1); + SET32_BITFIELDS(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE, cs_ticks - 1); + + SET32_BITFIELDS(&GET_TICK_DLY_REG(regs), SPI_TICK_DLY, tick_dly); } static void spi_sw_reset(struct mtk_spi_regs *regs) diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index b267aa0d92e4..4a81eae5dbce 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -8,6 +8,7 @@ #define SPI_BUS_NUMBER 1 #define GET_SCK_REG(x) x->spi_cfg0_reg +#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0) DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8) @@ -17,6 +18,6 @@ DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 24) DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) -DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) +DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 5bc70e5d36fb..47dee02161d7 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -8,6 +8,7 @@ #define SPI_BUS_NUMBER 6 #define GET_SCK_REG(x) x->spi_cfg2_reg +#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) @@ -18,7 +19,6 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) -DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) - +DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h index 15e7b9182f33..2588dcc311c5 100644 --- a/src/soc/mediatek/mt8186/include/soc/spi.h +++ b/src/soc/mediatek/mt8186/include/soc/spi.h @@ -13,6 +13,7 @@ #define SPI_BUS_NUMBER 6 #define GET_SCK_REG(x) x->spi_cfg2_reg +#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) @@ -23,7 +24,7 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) -DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) +DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29) enum { SPI_NOR_GPIO_SET0 = 0, diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h index db3ba216130f..28fe8390c8ab 100644 --- a/src/soc/mediatek/mt8192/include/soc/spi.h +++ b/src/soc/mediatek/mt8192/include/soc/spi.h @@ -8,6 +8,7 @@ #define SPI_BUS_NUMBER 8 #define GET_SCK_REG(x) x->spi_cfg2_reg +#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) @@ -18,6 +19,6 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) -DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) +DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8195/include/soc/spi.h b/src/soc/mediatek/mt8195/include/soc/spi.h index a74ed5643983..b51e503fd161 100644 --- a/src/soc/mediatek/mt8195/include/soc/spi.h +++ b/src/soc/mediatek/mt8195/include/soc/spi.h @@ -8,6 +8,7 @@ #define SPI_BUS_NUMBER 6 #define GET_SCK_REG(x) x->spi_cfg2_reg +#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) @@ -18,6 +19,6 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) -DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) +DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29) #endif |