4 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc
index 9a2ff7dc5a5d..2bef2e2596a2 100644
--- a/src/soc/mediatek/mt8188/Makefile.inc
+++ b/src/soc/mediatek/mt8188/Makefile.inc
@@ -6,6 +6,7 @@ all-y += ../common/uart.c
 
 bootblock-y += bootblock.c
 bootblock-y += ../common/mmu_operations.c
+bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
diff --git a/src/soc/mediatek/mt8188/bootblock.c b/src/soc/mediatek/mt8188/bootblock.c
index f48e78c309a3..770c6031dabf 100644
--- a/src/soc/mediatek/mt8188/bootblock.c
+++ b/src/soc/mediatek/mt8188/bootblock.c
@@ -2,8 +2,10 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu_operations.h>
+#include <soc/wdt.h>
 
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
+	mtk_wdt_init();
 }
diff --git a/src/soc/mediatek/mt8188/include/soc/wdt.h b/src/soc/mediatek/mt8188/include/soc/wdt.h
new file mode 100644
index 000000000000..39d5b179f38f
--- /dev/null
+++ b/src/soc/mediatek/mt8188/include/soc/wdt.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8188_WDT_H
+#define SOC_MEDIATEK_MT8188_WDT_H
+
+#include <soc/wdt_common.h>
+
+#define MTK_WDT_SPM_THERMAL_VAL 1
+
+DEFINE_BIT(MTK_WDT_SPM_THERMAL_EN, 0)
+DEFINE_BIT(MTK_WDT_THERMAL_EN, 17)
+DEFINE_BIT(MTK_WDT_THERMAL_IRQ, 17)
+
+#endif /* SOC_MEDIATEK_MT8188_WDT_H */
diff --git a/src/soc/mediatek/mt8188/wdt.c b/src/soc/mediatek/mt8188/wdt.c
new file mode 100644
index 000000000000..5218de39b839
--- /dev/null
+++ b/src/soc/mediatek/mt8188/wdt.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8188 Functional Specification
+ * Chapter number: 3.10.10
+ */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/wdt.h>
+
+#define MTK_WDT_CLR_STATUS_VAL 0x22
+
+DEFINE_BITFIELD(MTK_WDT_CLR_STATUS, 31, 24)
+
+void mtk_wdt_clr_status(void)
+{
+	SET32_BITFIELDS(&mtk_wdt->wdt_mode,
+			MTK_WDT_CLR_STATUS, MTK_WDT_CLR_STATUS_VAL);
+}