diff options
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra124/clock.c | 8 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/include/soc/clock.h | 4 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/verstage.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/clock.c | 4 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/clock.h | 5 |
5 files changed, 12 insertions, 11 deletions
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 9173e6200051..b9a4cd15ce49 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -247,17 +247,17 @@ static void init_utmip_pll(void) 1 << 8); /* (rst) phy_divm */ write32(&clk_rst->utmip_pll_cfg1, - CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ + DIV_ROUND_UP(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ 0 << 16 | /* PLLU pwrdn */ 0 << 14 | /* pll_enable pwrdn */ 0 << 12 | /* pll_active pwrdn */ - CEIL_DIV(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */ + DIV_ROUND_UP(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */ /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ write32(&clk_rst->utmip_pll_cfg2, 0 << 24 | /* SAMP_D/XDEV pwrdn */ - CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ - CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ + DIV_ROUND_UP(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ + DIV_ROUND_UP(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ 0 << 4 | /* SAMP_C/USB3 pwrdn */ 0 << 2 | /* SAMP_B/XHOST pwrdn */ 0 << 0); /* SAMP_A/USBD pwrdn */ diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index d08e26fb8004..bd32f0515f32 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -200,7 +200,7 @@ enum { * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you * will assign this to a u8, it gets nicely truncated for you. */ -#define CLK_DIVIDER(REF, FREQ) (div_round_up(((REF) * 2), (FREQ)) - 2) +#define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2) /* Calculate clock frequency value from reference and clock divider value * The discussion in the book is pretty lacking. @@ -253,7 +253,7 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div, */ #define clock_configure_i2c_scl_freq(device, src, freq) \ _clock_set_div(&clk_rst->clk_src_##device, #device, \ - div_round_up(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \ + DIV_ROUND_UP(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \ 0xffff, src) enum clock_source { /* Careful: Not true for all sources, always check TRM! */ diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index f8617a816614..d99f1a719e06 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -30,7 +30,7 @@ static void enable_cache(void) /* Whole space is uncached. */ mmu_config_range(0, 4096, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), DCACHE_WRITEBACK); mmu_disable_range(0, 1); dcache_mmu_enable(); diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 6ce2ba1291d1..5484d62b3863 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -330,7 +330,7 @@ static void init_utmip_pll(void) /* CFG1 */ u32 pllu_enb_ct = 0; - u32 phy_stb_ct = div_round_up(khz, 300); /* phy_stb_ct = 128 */ + u32 phy_stb_ct = DIV_ROUND_UP(khz, 300); /* phy_stb_ct = 128 */ write32(CLK_RST_REG(utmip_pll_cfg1), pllu_enb_ct << UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT | UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE | @@ -341,7 +341,7 @@ static void init_utmip_pll(void) /* CFG2 */ u32 pllu_stb_ct = 0; - u32 phy_act_ct = div_round_up(khz, 6400); /* phy_act_ct = 6 */ + u32 phy_act_ct = DIV_ROUND_UP(khz, 6400); /* phy_act_ct = 6 */ write32(CLK_RST_REG(utmip_pll_cfg2), phy_act_ct << UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT | pllu_stb_ct << UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT | diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index 50d72603ee7b..87d0850c7a5c 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -289,7 +289,7 @@ enum { * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you * will assign this to a u8, it gets nicely truncated for you. */ -#define CLK_DIVIDER(REF, FREQ) (div_round_up(((REF) * 2), (FREQ)) - 2) +#define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2) /* Calculate clock frequency value from reference and clock divider value * The discussion in the book is pretty lacking. @@ -324,7 +324,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div, src << CLK_SOURCE_SHIFT | div); } -#define get_i2c_clk_div(src,freq) (div_round_up(src, (freq) * (0x19 + 1) * 8) - 1) +#define get_i2c_clk_div(src, freq) \ + (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1) #define get_clk_div(src,freq) CLK_DIVIDER(src,freq) #define CLK_DIV_MASK 0xff #define CLK_DIV_MASK_I2C 0xffff |