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-rw-r--r--src/soc/amd/cezanne/Kconfig4
-rw-r--r--src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld3
-rw-r--r--src/soc/amd/picasso/Kconfig4
-rw-r--r--src/soc/amd/sabrina/Kconfig4
4 files changed, 2 insertions, 13 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 48944c858f16..8522d3fe2812 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -217,10 +217,6 @@ config CBFS_CACHE_SIZE
hex
default 0x40000 if CBFS_PRELOAD
-config RAMBASE
- hex
- default 0x10000000
-
config RO_REGION_ONLY
string
depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index f17043bf2728..4c2a74004874 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -111,7 +111,8 @@ SECTIONS
EARLY_RESERVED_DRAM_END(.)
- RAMSTAGE(CONFIG_RAMBASE, 8M)
+ /* Relocated at runtime in cbmem so the address does not matter. */
+ RAMSTAGE(64M, 8M)
}
#if ENV_BOOTBLOCK
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 84af18c23d8d..b005f9bd4d83 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -207,10 +207,6 @@ config VERSTAGE_SIZE
Sets the size of DRAM allocation for verstage in linker script if
running as a separate stage on x86.
-config RAMBASE
- hex
- default 0x10000000
-
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 3df7a4be6e1c..66719a6ce372 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -222,10 +222,6 @@ config CBFS_CACHE_SIZE
hex
default 0x40000 if CBFS_PRELOAD
-config RAMBASE
- hex
- default 0x10000000
-
config RO_REGION_ONLY
string
depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A