diff options
Diffstat (limited to 'src/soc')
201 files changed, 445 insertions, 445 deletions
diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 7937817316e0..47402b670bbf 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -60,7 +60,7 @@ static int agesa_locate_stage_file_ramstage(const char *name, .prog = &prog, }; - if (acpi_is_wakeup_s3() && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + if (acpi_is_wakeup_s3() && !CONFIG(NO_STAGE_CACHE)) { printk(BIOS_INFO, "AGESA: Loading stage from cache\n"); // There is no way to tell if this succeeded. stage_cache_load_stage(STAGE_REFCODE, &prog); @@ -71,7 +71,7 @@ static int agesa_locate_stage_file_ramstage(const char *name, if (rmodule_stage_load(&rmod_agesa) < 0) return -1; - if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + if (!CONFIG(NO_STAGE_CACHE)) { printk(BIOS_INFO, "AGESA: Saving stage to cache\n"); stage_cache_add(STAGE_REFCODE, &prog); } @@ -83,14 +83,14 @@ static int agesa_locate_stage_file_ramstage(const char *name, static int agesa_locate_stage_file(const char *name, struct region_device *rdev) { - if (!ENV_RAMSTAGE || !IS_ENABLED(CONFIG_AGESA_SPLIT_MEMORY_FILES)) + if (!ENV_RAMSTAGE || !CONFIG(AGESA_SPLIT_MEMORY_FILES)) return agesa_locate_stage_file_early(name, rdev); return agesa_locate_stage_file_ramstage(name, rdev); } static const char *get_agesa_cbfs_name(void) { - if (!IS_ENABLED(CONFIG_AGESA_SPLIT_MEMORY_FILES)) + if (!CONFIG(AGESA_SPLIT_MEMORY_FILES)) return CONFIG_AGESA_CBFS_NAME; if (!ENV_RAMSTAGE) return CONFIG_AGESA_PRE_MEMORY_CBFS_NAME; @@ -108,7 +108,7 @@ const void *agesawrapper_locate_module(const char name[8]) fname = get_agesa_cbfs_name(); - if (IS_ENABLED(CONFIG_AGESA_BINARY_PI_AS_STAGE)) + if (CONFIG(AGESA_BINARY_PI_AS_STAGE)) ret = agesa_locate_stage_file(fname, &rdev); else ret = agesa_locate_raw_file(fname, &rdev); @@ -119,7 +119,7 @@ const void *agesawrapper_locate_module(const char name[8]) file_size = region_device_sz(&rdev); /* Assume boot device is memory mapped so the mapping can leak. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); agesa = rdev_mmap_full(&rdev); diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 8bc0f3663bec..723b279aa3da 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -290,7 +290,7 @@ static int psp_load_blob(int type, void *addr) { int cmd_status; - if (!IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) { + if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); return PSPSTS_UNSUPPORTED; } diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 018975f098ed..1027ae0294af 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -59,7 +59,7 @@ AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* XHCI configuration */ - if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE)) + if (CONFIG(STONEYRIDGE_XHCI_ENABLE)) FchParams_env->Usb.Xhci0Enable = TRUE; else FchParams_env->Usb.Xhci0Enable = FALSE; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 3d7d833a9672..227fb7013624 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -91,7 +91,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; @@ -268,10 +268,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&gnvs->chromeos); gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl index 0b297fa1f56e..d4aabdb7afad 100644 --- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl +++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl @@ -16,7 +16,7 @@ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) -If (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { +If (CONFIG(HAVE_ACPI_RESUME)) { Store(0x0D, SSFG) } diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 37e22ac73da3..9239030d6c73 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -108,7 +108,7 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { - if (IS_ENABLED(CONFIG_STONEYRIDGE_UART)) + if (CONFIG(STONEYRIDGE_UART)) assert(CONFIG_UART_FOR_CONSOLE >= 0 && CONFIG_UART_FOR_CONSOLE <= 1); diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index a29c56c9dad3..1bd8cbf2f89b 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -159,7 +159,7 @@ static void earliest_ramstage(void *unused) romstage_handoff_is_resume(); if (!s3_resume) { post_code(0x46); - if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) + if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); post_code(0x47); diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 45e659504bf7..6572e1a2015b 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -29,7 +29,7 @@ static void per_core_finalize(void *unused) if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */ return; - if (IS_ENABLED(CONFIG_SMM_TSEG)) { + if (CONFIG(SMM_TSEG)) { mask = rdmsr(SMM_MASK_MSR); mask.lo |= SMM_TSEG_VALID; wrmsr(SMM_MASK_MSR, mask); diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 3212ec7cf7a8..15a41edce665 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -20,7 +20,7 @@ #include <arch/acpi.h> -#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE) +#if CONFIG(STONEYRIDGE_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index b1010142ef0f..613dd044f602 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -27,7 +27,7 @@ #define I2C_DEVICE_SIZE 0x00001000 #define I2C_DEVICE_COUNT 4 -#if IS_ENABLED(CONFIG_HPET_ADDRESS_OVERRIDE) +#if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 #endif #define HPET_BASE_ADDRESS 0xfed00000 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 68b5b08f1f00..e3475eebcb64 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -98,7 +98,7 @@ static void lpc_init(struct device *dev) /* Set up SERIRQ, enable continuous mode */ byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE); - if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) byte |= PM_SERIRQ_MODE; pm_write8(PM_SERIRQ_CONF, byte); diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index eddaba495192..8a875d9206cc 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -199,7 +199,7 @@ void check_mca(void) i, mci.cmask.hi, mci.cmask.lo); mci.bank = i; - if (IS_ENABLED(CONFIG_ACPI_BERT) + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 6c2637f26be9..927cce0c1f79 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -237,7 +237,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, current += hest->header.length; /* BERT */ - if (IS_ENABLED(CONFIG_ACPI_BERT) && bert_errors_present()) { + if (CONFIG(ACPI_BERT) && bert_errors_present()) { /* Skip the table if no errors are present. ACPI driver reports * a table with a 0-length region: * BERT: [Firmware Bug]: table invalid. diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index d805683f7114..edd5c2394e54 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -36,7 +36,7 @@ uintptr_t restore_top_of_low_cacheable(void) return biosram_read32(BIOSRAM_CBMEM_TOP); } -#if IS_ENABLED(CONFIG_ACPI_BERT) +#if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 #define BERT_REGION_MAX_SIZE 0x100000 #else @@ -49,7 +49,7 @@ uintptr_t restore_top_of_low_cacheable(void) void bert_reserved_region(void **start, size_t *size) { - if (IS_ENABLED(CONFIG_ACPI_BERT)) + if (CONFIG(ACPI_BERT)) *start = cbmem_top(); else start = NULL; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 42f6f8a758fd..f2263b7aa913 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -93,7 +93,7 @@ asmlinkage void car_stage_entry(void) console_init(); - if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) + if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) load_smu_fw1(); mainboard_romstage_entry(s3_resume); @@ -132,7 +132,7 @@ asmlinkage void car_stage_entry(void) msr_t sys_cfg = rdmsr(SYSCFG_MSR); sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; wrmsr(SYSCFG_MSR, sys_cfg); - if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)) + if (CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); @@ -192,7 +192,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams) if (!dev || !dev->chip_info) { printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); /* In case of a BIOS error, only attempt to set UMA. */ - PostParams->MemConfig.UmaMode = IS_ENABLED(CONFIG_GFXUMA) ? + PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; return; } diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 657ff493dc77..c053d909f749 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -103,7 +103,7 @@ static void sb_apmc_smi_handler(void) acpi_write32(MMIO_ACPI_PM1_CNT_BLK, reg32); break; case APM_CNT_ELOG_GSMI: - if (IS_ENABLED(CONFIG_ELOG_GSMI)) + if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; } @@ -156,7 +156,7 @@ static void sb_slp_typ_handler(void) if (slp_typ >= ACPI_S3) { /* Sleep Type Elog S3, S4, and S5 entry */ - if (IS_ENABLED(CONFIG_ELOG_GSMI)) + if (CONFIG(ELOG_GSMI)) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); wbinvd(); @@ -183,7 +183,7 @@ static void sb_slp_typ_handler(void) * it and continue normal path. S3 will fail and the wake event * becomes a SCI. */ - if (IS_ENABLED(CONFIG_ELOG_GSMI)) { + if (CONFIG(ELOG_GSMI)) { reg16 = acpi_read16(MMIO_ACPI_PM1_EN); reg16 &= acpi_read16(MMIO_ACPI_PM1_STS); if (reg16) @@ -197,7 +197,7 @@ static void sb_slp_typ_handler(void) elog_add_extended_event( ELOG_SLEEP_PENDING_GPE0_WAKE, reg32); - } /* if (IS_ENABLED(CONFIG_ELOG_GSMI)) */ + } /* if (CONFIG(ELOG_GSMI)) */ /* * An IO cycle is required to trigger the STPCLK/STPGNT diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 069fc7879c76..2f32c5c86eb3 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -76,7 +76,7 @@ static inline int sb_ide_enable(void) void SetFchResetParams(FCH_RESET_INTERFACE *params) { const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); + params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); if (dev && dev->enabled) { params->SataEnable = sb_sata_enable(); params->IdeEnable = sb_ide_enable(); @@ -553,7 +553,7 @@ static void sb_lpc_early_setup(void) dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN; pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); - if (IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)) { + if (CONFIG(STONEYRIDGE_LEGACY_FREE)) { /* Decode SIOs at 2E/2F and 4E/4F */ dword = pci_read_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); @@ -742,7 +742,7 @@ static void sb_init_acpi_ports(void) /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */ pm_write16(PM_ACPI_SMI_CMD, APM_CNT); configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); @@ -804,7 +804,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) static void sb_log_pm1_status(uint16_t pm1_sts) { - if (!IS_ENABLED(CONFIG_ELOG)) + if (!CONFIG(ELOG)) return; if (pm1_sts & WAK_STS) @@ -952,7 +952,7 @@ void southbridge_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; - if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE)) + if (CONFIG(MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index 409b9b190418..e6b1a36d1664 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -29,7 +29,7 @@ #include <soc/southbridge.h> #include <soc/pci_devs.h> -#define SPI_DEBUG_DRIVER IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) static uintptr_t spibar; diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 2358d71c5717..98166b056f7d 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -370,7 +370,7 @@ static void soc_init(struct device *dev) /* Init ECAM, MDIO, PEM, PHY, QLM ... */ bdk_boot(); - if (IS_ENABLED(CONFIG_PAYLOAD_FIT_SUPPORT)) { + if (CONFIG(PAYLOAD_FIT_SUPPORT)) { struct device_tree_fixup *dt_fixup; dt_fixup = malloc(sizeof(*dt_fixup)); @@ -381,7 +381,7 @@ static void soc_init(struct device *dev) } } - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) soc_init_atf(); } diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index a512dffa0082..c3f086685949 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -38,17 +38,17 @@ void bootblock_main(const uint64_t reg_x0, init_timer(); - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)) + if (CONFIG(COLLECT_TIMESTAMPS)) base_timestamp = timestamp_get(); /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0) + if (CONFIG(COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0) timestamp_init(base_timestamp); bootblock_soc_early_init(); bootblock_mainboard_early_init(); - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index c87b51cfbe12..07cb2adef790 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -92,10 +92,10 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&gnvs->chromeos); gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; @@ -128,7 +128,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); } - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); } diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index 2475db39a102..d1402d9651c6 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -30,7 +30,7 @@ Method(_PRT) Package(){0x000FFFFF, 0, 0, CSE_INT}, Package(){0x0011FFFF, 0, 0, ISH_INT}, Package(){0x0012FFFF, 0, 0, SATA_INT}, -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) Package(){0x000CFFFF, 0, 0, CNVI_INT}, Package(){0x0013FFFF, 0, 0, PIRQF_INT}, Package(){0x0013FFFF, 1, 0, PIRQF_INT}, diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 799778bc3c00..7c9c873ddbbc 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -45,6 +45,6 @@ #include <soc/intel/common/acpi/pci_osc.asl> /* SGX */ -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> #endif diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 9f7304bb57ff..a7317fe82bfd 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -34,7 +34,7 @@ Device (XHCI) { /* Root Hub */ Name (_ADR, Zero) -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) #include "xhci_glk_ports.asl" #else #include "xhci_apl_ports.asl" diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index bb5eff8c8bb4..ac6903a9d211 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -38,7 +38,7 @@ #include <timestamp.h> static const struct pad_config tpm_spi_configs[] = { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ #else PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ @@ -95,10 +95,10 @@ void bootblock_soc_early_init(void) pmc_global_reset_enable(0); /* Prepare UART for serial console. */ - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); - if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)) + if (CONFIG(TPM_ON_FAST_SPI)) tpm_enable(); enable_pm_timer_emulation(); @@ -116,7 +116,7 @@ void bootblock_soc_early_init(void) /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I * speculatively fetches a line that is sitting in the L1D. */ - if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) { + if (CONFIG(PAGING_IN_CACHE_AS_RAM)) { paging_set_nxe(1); paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 6b8479d352ec..30a537b6758d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -124,7 +124,7 @@ const char *soc_acpi_name(const struct device *dev) case 6: return "HS07"; case 7: return "HS08"; case 8: - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GLK)) return "HS09"; } break; @@ -300,7 +300,7 @@ static void set_power_limits(void) uint32_t tdp, min_power, max_power; uint32_t pl2_val; - if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip the RAPL settings.\n"); return; } @@ -527,7 +527,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) case PCH_DEVFN_SMBUS: silconfig->SmbusEnable = 0; break; -#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if !CONFIG(SOC_INTEL_GLK) case SA_DEVFN_IPU: silconfig->IpuEn = 0; break; @@ -558,7 +558,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig) static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* GLK FSP does not have these +#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */ uint8_t port; @@ -597,7 +597,7 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config static void glk_fsp_silicon_init_params_cb( struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) uint8_t port; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { @@ -730,7 +730,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Disable monitor mwait since it is broken due to a hardware bug * without a fix. Specific to Apollolake. */ - if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (!CONFIG(SOC_INTEL_GLK)) silconfig->MonitorMwaitEnable = 0; silconfig->SkipMpInit = !chip_get_fsp_mp_init(); @@ -746,7 +746,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; /* Bios config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GLK)) glk_fsp_silicon_init_params_cb(cfg, silconfig); else apl_fsp_silicon_init_params_cb(cfg, silconfig); @@ -847,7 +847,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) * Override GLK xhci clock gating register(XHCLKGTEN) to * mitigate usb device suspend and resume failure. */ - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) { + if (CONFIG(SOC_INTEL_GLK)) { uint32_t *cfg; const struct resource *res; uint32_t reg; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index a08f1f0352c1..741e08c9b770 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -46,7 +46,7 @@ #include <soc/pm.h> static const struct reg_script core_msr_script[] = { -#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if !CONFIG(SOC_INTEL_GLK) /* Enable C-state and IO/MWAIT redirect */ REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL, (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK @@ -73,7 +73,7 @@ void soc_core_init(struct device *cpu) /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) || + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || acpi_get_sleep_type() == ACPI_S5) mca_configure(NULL); @@ -87,20 +87,20 @@ void soc_core_init(struct device *cpu) enable_pm_timer_emulation(); /* Configure Core PRMRR for SGX. */ - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) prmrr_core_configure(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ - if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); cpu_disable_eist(); - } else if (IS_ENABLED(CONFIG_APL_SET_MIN_CLOCK_RATIO)) { + } else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) { cpu_set_p_state_to_min_clock_ratio(); cpu_disable_eist(); } } -#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) static void soc_init_core(struct device *cpu) { soc_core_init(cpu); @@ -139,7 +139,7 @@ static struct smm_relocation_attrs relo_attrs; /* * Do essential initialization tasks before APs can be fired up. * - * IF (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) - + * IF (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) - * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP, * that are set prior to ramstage. * Real MTRRs are programmed after resource allocation. @@ -155,7 +155,7 @@ static struct smm_relocation_attrs relo_attrs; */ static void pre_mp_init(void) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) { fsps_load(romstage_handoff_is_resume()); return; } @@ -163,7 +163,7 @@ static void pre_mp_init(void) x86_mtrr_check(); } -#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) { msr_t msr; @@ -247,7 +247,7 @@ static void post_mp_init(void) { smm_southbridge_enable(PWRBTN_EN | GBL_EN); - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) mp_run_on_all_cpus(sgx_configure, NULL, 2000); } @@ -270,13 +270,13 @@ void soc_init_cpus(struct bus *cpu_bus) void apollolake_init_cpus(struct device *dev) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) return; soc_init_cpus(dev->link_list); /* Temporarily cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && - IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && + CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 85a2b197dfcb..82226ecf4396 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -222,7 +222,7 @@ static void dump_cse_version(void *unused) * Print ME version only if UART debugging is enabled. Else, it takes * ~0.6 second to talk to ME and get this information. */ - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) return; msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN; diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 9be598f61abe..a05d6087be2b 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -35,14 +35,14 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *const dev) { - if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) + if (CONFIG(RUN_FSP_GOP)) return; uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { int lightup_ok; gma_gfxinit(&lightup_ok); diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 20d2993ce23d..939c449159a4 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -17,7 +17,7 @@ #ifndef _SOC_APL_GPIO_H_ #define _SOC_APL_GPIO_H_ -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) #include <soc/gpio_glk.h> #else #include <soc/gpio_apl.h> diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index 264704c7557b..d591c21b586d 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -20,7 +20,7 @@ /* * Port ids. */ -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) #define PID_GPIO_AUDIO 0xC9 #define PID_GPIO_SCC 0xC8 #else diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 61c97cebb587..d3538342b02d 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -71,7 +71,7 @@ #define SMI_EOS 1 #define SMI_GBL 0 -#if IS_ENABLED(CONFIG_SOC_ESPI) +#if CONFIG(SOC_ESPI) #define ESPI_SMI_EN (1 << SMI_ESPI) /* Valid for GLK with ESPI */ #else #define ESPI_SMI_EN 0 @@ -190,7 +190,7 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4 + 4*(x)) -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) #define PMC_GPE_AUDIO_31_0 9 #define PMC_GPE_N_95_64 8 #define PMC_GPE_N_63_32 7 diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index a20b82ae0a0e..ceed8f268f10 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -43,8 +43,8 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) } static const struct pad_config lpc_gpios[] = { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) -#if !IS_ENABLED(CONFIG_SOC_ESPI) +#if CONFIG(SOC_INTEL_GLK) +#if !CONFIG(SOC_ESPI) PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT0 */ @@ -69,7 +69,7 @@ static const struct pad_config lpc_gpios[] = { * will keep LPC Controller awake and prevent S0ix entry */ PAD_NC(GPIO_154, NONE), -#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */ +#endif /* !CONFIG(SOC_ESPI) */ #else PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 889bbde66dd5..038fa9fb2b5c 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -166,7 +166,7 @@ static const struct fsp_speed_profiles glk_profile = { static const struct fsp_speed_profiles *get_fsp_profile(void) { - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GLK)) return &glk_profile; else return &apl_profile; diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index a69a5cb11692..ba1433c53b79 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -30,7 +30,7 @@ void *cbmem_top(void) const config_t *config; void *tolum = (void *)sa_get_tseg_base(); - if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (!CONFIG(SOC_INTEL_GLK)) return tolum; dev = dev_find_slot(0, PCH_DEVFN_LPC); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ad4b5b0b2f51..bef7052cea6e 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -95,7 +95,7 @@ static void soc_early_romstage_init(void) pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | P2SB_HPTC_ADDRESS_ENABLE); - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); } @@ -159,7 +159,7 @@ static bool punit_init(void) PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | PUINT_THERMAL_DEVICE_IRQ_LOCK; - if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) { + if (!CONFIG(SOC_INTEL_GLK)) { data = MCHBAR32(0x7818); data &= 0xFFFFE01F; data |= 0x20 | 0x200; @@ -277,8 +277,8 @@ asmlinkage void car_stage_entry(void) static void fill_console_params(FSPM_UPD *mupd) { - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) { + if (CONFIG(CONSOLE_SERIAL)) { + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) { mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; /* use MMIO port type */ @@ -287,7 +287,7 @@ static void fill_console_params(FSPM_UPD *mupd) mupd->FspmConfig.SerialDebugPortStrideSize = 2; /* used only for port type set to external */ mupd->FspmConfig.SerialDebugPortAddress = 0; - } else if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) { + } else if (CONFIG(DRIVERS_UART_8250IO)) { /* use external UART for debug */ mupd->FspmConfig.SerialDebugPortDevice = 3; /* use I/O port type */ @@ -320,7 +320,7 @@ static void check_full_retrain(const FSPM_UPD *mupd) static void soc_memory_init_params(FSPM_UPD *mupd) { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); assert(dev != NULL); @@ -351,7 +351,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) static void parse_devicetree_setting(FSPM_UPD *m_upd) { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK); if (!dev) return; @@ -368,7 +368,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) fill_console_params(mupd); - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); mainboard_memory_init_params(mupd); @@ -385,7 +385,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) * as designed. */ mupd->FspmConfig.SkipCseRbp = - IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); + CONFIG(BOOT_DEVICE_MEMORY_MAPPED); /* * Converged Security Engine (CSE) has secure storage functionality. @@ -407,7 +407,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) { /* Assume leaking is ok. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); } diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index cbb0c8c29a76..7a3400ed3b20 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -50,7 +50,7 @@ const smi_handler_t southbridge_smi[32] = { [GPIO_SMI_STS] = smihandler_southbridge_gpi, [TCO_SMI_STS] = smihandler_southbridge_tco, [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, -#if IS_ENABLED(CONFIG_SOC_ESPI) +#if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, #endif }; diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 875bc49575d2..66a1a1abcc13 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -28,7 +28,7 @@ /* UART pad configuration. Support RXD and TXD for now. */ const struct uart_gpio_pad_config uart_gpio_pads[] = { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) { .console_index = 0, .gpios = { diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 666a9daaf3d9..c322cce0adc1 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -83,15 +83,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index bc8e8776970a..09d13221b327 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -281,7 +281,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index 827c706ccad3..d20859d05501 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -25,7 +25,7 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); void set_max_freq(void); void southcluster_enable_dev(struct device *dev); -#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB) +#if CONFIG(HAVE_REFCODE_BLOB) void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index b65c6809a961..3e8b6a27ef85 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -39,7 +39,7 @@ void punit_init(void); void set_max_freq(void); int early_spi_read_wpsr(u8 *sr); -#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1) +#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); #else static inline void byt_config_com1_and_enable(void) { } diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 0869c7b656bb..5f33c86c9ba0 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -131,7 +131,7 @@ static void nc_read_resources(struct device *dev) reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 550f8724c3bf..dfc53667336e 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -112,7 +112,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->version = MRC_PARAMS_VER; mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; - mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); + mp->rmt_enabled = CONFIG(MRC_RMT); /* Default to 2GiB IO hole. */ if (!mp->io_hole_mb) @@ -124,7 +124,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->saved_data_size = region_device_sz(&rdev); mp->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); } else if (prev_sleep_state == ACPI_S3) { /* If waking from S3 and no cache then. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -157,7 +157,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) if (prev_sleep_state != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { - #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + #if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7ea1443ed665..5621dd16eb8c 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include <elog.h> @@ -193,7 +193,7 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: @@ -224,7 +224,7 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) if (prev_sleep_state != ACPI_S3) boot_count_increment(); #endif diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index c722f5c1f203..1bc9ed1c3425 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -113,7 +113,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -209,7 +209,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -242,7 +242,7 @@ static void finalize(void) } finalize_done = 1; -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -347,7 +347,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -373,7 +373,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 9dd89d2a8d6b..1faf6516b3ad 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -134,7 +134,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 4ace22aab90f..dbd29503c777 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -89,15 +89,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif @@ -492,12 +492,12 @@ unsigned long southcluster_write_acpi_tables(struct device *device, acpi_header_t *ssdt2; global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!IS_ENABLED(CONFIG_DISABLE_HPET)) { + if (!CONFIG(DISABLE_HPET)) { current = acpi_write_hpet(device, current, rsdp); current = acpi_align_current(current); } - if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) { + if (CONFIG(INTEL_GMA_ADD_VBT)) { igd_opregion_t *opregion; printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); @@ -543,7 +543,7 @@ void southcluster_inject_dsdt(struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* Fill in the Wifi Region id */ - if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN)) + if (CONFIG(HAVE_REGULATORY_DOMAIN)) gnvs->cid1 = wifi_regulatory_domain(); else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 067b05f6de31..6b2ececc4056 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -48,7 +48,7 @@ Device (LPCB) }) } -#if !IS_ENABLED(CONFIG_DISABLE_HPET) +#if !CONFIG(DISABLE_HPET) Device (HPET) { Name (_HID, EISAID("PNP0103")) diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 023a5b9ee04b..16751fbadd16 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -67,7 +67,7 @@ static void gfx_init(struct device *dev) printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - if (!IS_ENABLED(CONFIG_RUN_FSP_GOP)) { + if (!CONFIG(RUN_FSP_GOP)) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 5d8c332feb5f..5063342955d1 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -242,7 +242,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d2653f3093b8..207c843d52f6 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -37,7 +37,7 @@ void smm_region(void **start, size_t *size) size_t mmap_region_granularity(void) { /* Align to TSEG size when SMM is in use, and 8MiB by default */ - return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? smm_region_size() + return CONFIG(HAVE_SMI_HANDLER) ? smm_region_size() : 8 << 20; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index c54c2c8f3c71..92674486973c 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -165,7 +165,7 @@ static void nc_read_resources(struct device *dev) size_k = RES_IN_KIB(0x00100000); mmio_resource(dev, index++, base_k, size_k); - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); } diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 5fe35505098d..e4180641a624 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -161,7 +161,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: @@ -229,7 +229,7 @@ void soc_memory_init_params(struct romstage_params *params, config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 1f02269cec0b..a72330915eef 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -153,7 +153,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -259,7 +259,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -292,7 +292,7 @@ static void finalize(void) } finalize_done = 1; -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -345,7 +345,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -368,7 +368,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index fa22cf7c06fd..c87232dd9289 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -119,7 +119,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(void *addr) { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index aa2dd2ad8ebd..e51c9bf7cef6 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -169,15 +169,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index aab8045f3f50..6383e15e79fb 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -30,7 +30,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, #endif }; diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 964534831dc2..1adbbc8aa220 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -56,7 +56,7 @@ const struct reg_script system_agent_finalize_script[] = { }; const struct reg_script pch_finalize_script[] = { -#if !IS_ENABLED(CONFIG_SPI_CONSOLE) +#if !CONFIG(SPI_CONSOLE) /* Set SPI opcode menu */ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP, SPI_OPPREFIX), diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 94ec3a72f890..319549df1e63 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -512,7 +512,7 @@ static void igd_init(struct device *dev) /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) if (display_init_required() || vboot_wants_oprom()) mdelay(CONFIG_PRE_GRAPHICS_DELAY); #else diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 7292bcf38664..71c7999e5b31 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -23,7 +23,7 @@ void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); void broadwell_pch_enable_dev(struct device *dev); -#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB) +#if CONFIG(HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); #else static inline void broadwell_run_reference_code(void) { } diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 63db9aaafcfc..c831c2c5bc6a 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -219,7 +219,7 @@ static const struct reg_script pch_misc_init_script[] = { REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), #endif REG_SCRIPT_END @@ -429,7 +429,7 @@ static void pch_cg_init(struct device *dev) static void pch_set_acpi_mode(void) { -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); @@ -621,7 +621,7 @@ static unsigned long broadwell_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)) + if (CONFIG(INTEL_PCH_UART_CONSOLE)) current = acpi_write_dbg2_pci_uart(rsdp, current, (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ? PCH_DEV_UART1 : PCH_DEV_UART0, diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 73317e3e714d..dd5e5b870ca1 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -40,7 +40,7 @@ #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -58,7 +58,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u8 *mei_base_address; -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -483,7 +483,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) vers_name->hotfix_version, vers_name->build_version); } -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -703,7 +703,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -792,7 +792,7 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -804,7 +804,7 @@ static void intel_me_print_mbp(me_bios_payload *mbp_data) { me_print_fw_version(mbp_data->fw_version_name); -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) me_print_fwcaps(mbp_data->fw_capabilities); #endif @@ -912,7 +912,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) } /* Dump out the MBP contents. */ -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); for (i = 0; i < mbp->header.mbp_size - 1; i++) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 3fd5ea4f10d8..32135eedbb2c 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -555,7 +555,7 @@ static void pch_pcie_early(struct device *dev) pci_update_config8(dev, 0xf5, 0x0f, 0); /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - if (IS_ENABLED(CONFIG_PCIEXP_AER)) + if (CONFIG(PCIEXP_AER)) pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); else @@ -563,7 +563,7 @@ static void pch_pcie_early(struct device *dev) (1 << 29)); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + if (CONFIG(PCIEXP_L1_SUB_STATE)) pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); else pci_update_config32(dev, 0x200, ~0xfffff, 0); diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 291d5eb9ea66..ca22b4ef5b20 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -57,7 +57,7 @@ static int prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index acb435bce013..04657aebd8ca 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -24,7 +24,7 @@ #include <memory_info.h> #include <mrc_cache.h> #include <string.h> -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #endif @@ -57,7 +57,7 @@ void raminit(struct pei_data *pei_data) pei_data->saved_data_size = region_device_sz(&rdev); pei_data->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); } else if (pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -104,7 +104,7 @@ void raminit(struct pei_data *pei_data) if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 9aa31b85c1ab..2531665f1fb5 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -123,7 +123,7 @@ void romstage_common(struct romstage_params *params) params->pei_data->boot_mode = params->power_state->prev_sleep_state; -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) if (params->power_state->prev_sleep_state != ACPI_S3) boot_count_increment(); #endif diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 0330acb91b4e..59fb4f7a7e2f 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -41,7 +41,7 @@ static void serialio_enable_d3hot(struct resource *res) static int serialio_uart_is_debug(struct device *dev) { -#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) +#if CONFIG(INTEL_PCH_UART_CONSOLE) switch (dev->path.pci.devfn) { case PCH_DEVFN_UART0: /* UART0 */ return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0); @@ -278,7 +278,7 @@ static void serialio_set_resources(struct device *dev) { pci_dev_set_resources(dev); -#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) +#if CONFIG(INTEL_PCH_UART_CONSOLE) /* Update UART base address if used for debug */ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 9f5d81dc31b7..b36b99dd4e7f 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -178,7 +178,7 @@ static void southbridge_smi_sleep(void) /* USB sleep preparations */ usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -292,7 +292,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -325,7 +325,7 @@ static void finalize(void) } finalize_done = 1; -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -371,7 +371,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -390,7 +390,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 21417cf8282b..d8127577db17 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -133,7 +133,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 391268818143..aef1d1cd4482 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -384,7 +384,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); *resource_cnt = index; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 127d9c8b64d9..639f6c6f90dd 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -204,14 +204,14 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) /* Update the mem console pointer. */ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; } else diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 1806e75e87dd..cdfff911b8a2 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -112,7 +112,7 @@ Scope (\_SB.PCI0) { And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) -#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) +#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to Native */ GPMO(SD_PWR_EN_PIN, 0x1) #endif @@ -126,7 +126,7 @@ Scope (\_SB.PCI0) { Or (PMCR, 0x0003, PMCR) Store (PMCR, ^TEMP) -#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) +#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to GPIO control */ GPMO(SD_PWR_EN_PIN, 0x0) diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index ae8de6a1df34..d9ff70b6bca7 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -30,7 +30,7 @@ #include "scs.asl" /* GPIO controller */ -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include "gpio_cnp_h.asl" #else #include "gpio.asl" diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 08a13ea8600f..5555969289fa 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -20,7 +20,7 @@ #include <soc/iomap.h> #include <soc/pch.h> -#if IS_ENABLED(CONFIG_FSP_CAR) +#if CONFIG(FSP_CAR) #include <FsptUpd.h> const FSPT_UPD temp_ram_init_params = { @@ -53,7 +53,7 @@ void bootblock_soc_early_init(void) bootblock_pch_early_init(); bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index 3ebe1e48e6e1..f60f31999975 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -21,7 +21,7 @@ void bootblock_cpu_init(void) { /* Temporarily cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && - IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && + CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 018ccfc46707..1c7fd7f082f0 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -162,7 +162,7 @@ void pch_early_iorange_init(void) LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index a643954a91d0..993e7f3d4adc 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -29,7 +29,7 @@ #include <soc/ramstage.h> #include <string.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -195,7 +195,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, - #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index ab7c765043e6..3e4bafc3220a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -30,7 +30,7 @@ #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include <soc/gpio_defs_cnp_h.h> #else #include <soc/gpio_defs.h> @@ -107,7 +107,7 @@ struct soc_intel_cannonlake_config { enum { SaGv_Disabled, SaGv_FixedLow, -#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) SaGv_FixedMid, #endif SaGv_FixedHigh, diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index e97b5711e87b..db001b82aead 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -90,7 +90,7 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, die("spd.bin not found or incorrect index\n"); spd_data_len = region_device_sz(&spd_rdev); /* Memory leak is ok since we have memory mapped boot media */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); } diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 19ff171eb8e8..6bedb8139036 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -497,7 +497,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * have this check, where CNL CPU die is not based on KBL CPU * so skip this check for CNL. */ - if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)) + if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)) return 0; /* diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 1ebde35e05f4..318b8a25ae95 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -213,7 +213,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } else { params->ScsSdCardEnabled = dev->enabled; params->SdCardPowerEnableActiveHigh = - IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); + CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); } dev = dev_find_slot(0, PCH_DEVFN_UFS); diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 2b3c9007a4a8..015220d249dc 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -54,7 +54,7 @@ void graphics_soc_init(struct device *dev) * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) + if (CONFIG(INTEL_GMA_ADD_VBT)) return; /* IGD needs to Bus Master */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index 718372ddc19c..e7056ebcec4d 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -16,7 +16,7 @@ #ifndef _SOC_CANNONLAKE_GPIO_H_ #define _SOC_CANNONLAKE_GPIO_H_ -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include <soc/gpio_defs_cnp_h.h> #define CROS_GPIO_DEVICE_NAME "INT3450:00" #else diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index c3957d39c8a0..95cca65ab266 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -116,7 +116,7 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 #define PMC_GPP_C 0x2 diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index 9121ac3031f0..e38c3381d897 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -50,7 +50,7 @@ struct smm_relocation_params { /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 5dffb8197ee4..7c6025cb756e 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -227,7 +227,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else lpc_set_serirq_mode(SERIRQ_QUIET); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 8ffda2a57ba3..b2dd26dcf097 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -147,7 +147,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, traditional_mem_base -= sa_get_tseg_size(); /* Get DPR size */ - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) traditional_mem_base -= sa_get_dpr_size(); /* Traditional Area Size */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index b8b2c1798c7a..5597c4f23051 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -34,7 +34,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; - if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)) + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) m_cfg->UserBd = BOARD_TYPE_DESKTOP; else m_cfg->UserBd = BOARD_TYPE_ULT_ULX; @@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->VmxEnable = 0; else m_cfg->VmxEnable = config->VmxEnable; -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 5f9e0f82afbf..643fad645faf 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -93,7 +93,7 @@ void smihandler_soc_at_finalize(void) void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index d3860dd76c67..6c52bbfd7754 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -13,11 +13,11 @@ * GNU General Public License for more details. */ -#if IS_ENABLED(CONFIG_ACPI_CONSOLE) +#if CONFIG(ACPI_CONSOLE) #include <soc/iomap.h> -Name (UFLG, IS_ENABLED(CONFIG_CONSOLE_SERIAL)) +Name (UFLG, CONFIG(CONSOLE_SERIAL)) Method (LURT, 1, Serialized) { @@ -57,7 +57,7 @@ Method (APRT, 1, Serialized) } Store (INDX, LENG) /* Length of the String */ -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) +#if CONFIG(DRIVERS_UART_8250MEM_32) OperationRegion (UBAR, SystemMemory, UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE), 24) Field (UBAR, AnyAcc, NoLock, Preserve) diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 01913b51c5dd..bdc0d5c15c9b 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -34,7 +34,7 @@ Method (_PTS, 1) { Store (POST_OS_ENTER_PTS, DBG0) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) +#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) /* Call EC _PTS handler */ \_SB.PCI0.LPCB.EC0.PTS (Arg0) #endif @@ -46,7 +46,7 @@ Method (_WAK, 1) { Store (POST_OS_ENTER_WAKE, DBG0) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) +#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) /* Call EC _WAK handler */ \_SB.PCI0.LPCB.EC0.WAK (Arg0) #endif diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 002774400342..e311ae62107e 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -180,7 +180,7 @@ uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, return generic_pm1_en; } -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) +#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* * Save wake source information for calculating ACPI _SWS values * @@ -452,7 +452,7 @@ void generate_cpu_entries(struct device *device) acpigen_write_processor_cnot(cores_per_package); } -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) +#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* Save wake source data for ACPI _SWS methods in NVS */ static void acpi_save_wake_source(void *unused) { diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 17b8dc063ce3..d3ee671bef26 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -167,11 +167,11 @@ clear_var_mtrr: invd mov %eax, %cr0 -#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) +#if CONFIG(INTEL_CAR_NEM) jmp car_nem -#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +#elif CONFIG(INTEL_CAR_CQOS) jmp car_cqos -#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +#elif CONFIG(INTEL_CAR_NEM_ENHANCED) jmp car_nem_enhanced #else jmp .halt_forever /* In case nothing has selected */ @@ -221,7 +221,7 @@ fixed_mtrr_list: .word MTRR_FIX_4K_F8000 fixed_mtrr_list_size = . - fixed_mtrr_list -#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) +#if CONFIG(INTEL_CAR_NEM) .global car_nem car_nem: /* Disable cache eviction (setup stage) */ @@ -252,7 +252,7 @@ car_nem: jmp car_init_done -#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +#elif CONFIG(INTEL_CAR_CQOS) .global car_cqos car_cqos: /* @@ -356,7 +356,7 @@ car_cqos: jmp car_init_done -#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +#elif CONFIG(INTEL_CAR_NEM_ENHANCED) .global car_nem_enhanced car_nem_enhanced: /* Disable cache eviction (setup stage) */ diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index a4d16e8022cf..ab7886cb36c1 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -23,7 +23,7 @@ .global chipset_teardown_car chipset_teardown_car: -#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +#if CONFIG(PAGING_IN_CACHE_AS_RAM) /* * Since Page table is located in CAR, disable paging before CAR * teardown. Also clear CR3 and CR4.PAE. @@ -50,7 +50,7 @@ chipset_teardown_car: and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr -#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) +#if CONFIG(INTEL_CAR_NEM) .global car_nem_teardown car_nem_teardown: @@ -65,7 +65,7 @@ car_nem_teardown: and $(~(1 << 0)), %eax wrmsr -#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +#elif CONFIG(INTEL_CAR_CQOS) .global car_cqos_teardown car_cqos_teardown: @@ -86,7 +86,7 @@ car_cqos_teardown: and $~IA32_PQR_ASSOC_MASK, %edx wrmsr -#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +#elif CONFIG(INTEL_CAR_NEM_ENHANCED) .global car_nem_enhanced_teardown car_nem_enhanced_teardown: diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index d196f6195fa6..2e3b99e16759 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -157,7 +157,7 @@ void fast_spi_lock_bar(void) void *spibar = fast_spi_get_bar(); uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN; - if (IS_ENABLED(CONFIG_FAST_SPI_DISABLE_WRITE_STATUS)) + if (CONFIG(FAST_SPI_DISABLE_WRITE_STATUS)) hsfs |= SPIBAR_HSFSTS_WRSDIS; write16(spibar + SPIBAR_HSFSTS_CTL, hsfs); diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d77e052c96d1..0065a6c54faf 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -35,7 +35,7 @@ PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) #define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \ PAD_CFG1_PULL_MASK | \ PAD_CFG1_TOL_MASK | \ @@ -190,7 +190,7 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, if (ENV_SMM) return; - if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) return; int irq; @@ -276,7 +276,7 @@ static void gpio_configure_pad(const struct pad_config *cfg) /* Patch GPIO settings for SoC specifically */ soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf); - if (IS_ENABLED(CONFIG_DEBUG_GPIO)) + if (CONFIG(DEBUG_GPIO)) printk(BIOS_DEBUG, "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x" " : 0x%08x]\n", @@ -411,7 +411,7 @@ uint16_t gpio_acpi_pin(gpio_t gpio_num) const struct pad_community *comm; size_t group, pin; - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES)) return relative_pad_in_comm(gpio_get_community(gpio_num), gpio_num); @@ -489,7 +489,7 @@ void gpi_clear_get_smi_status(struct gpi_status *sts) comm++; } - if (IS_ENABLED(CONFIG_DEBUG_SMI)) + if (CONFIG(DEBUG_SMI)) print_gpi_status(sts); } @@ -560,7 +560,7 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d) MISCCFG_GPE0_DW1_MASK | MISCCFG_GPE0_DW0_MASK); - if (IS_ENABLED(CONFIG_DEBUG_GPIO)) + if (CONFIG(DEBUG_GPIO)) printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n", misccfg_mask, misccfg_value); comm = soc_gpio_get_community(&gpio_communities); diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 3e58d60e2e30..81eb7eedec27 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -355,7 +355,7 @@ static uint32_t gspi_csctrl_state_v1(uint32_t pol, enum cs_assert cs_assert) static uint32_t gspi_csctrl_state(uint32_t pol, enum cs_assert cs_assert) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)) return gspi_csctrl_state_v2(pol, cs_assert); return gspi_csctrl_state_v1(pol, cs_assert); @@ -379,7 +379,7 @@ static uint32_t gspi_csctrl_polarity_v1(enum spi_polarity active_pol) static uint32_t gspi_csctrl_polarity(enum spi_polarity active_pol) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)) return gspi_csctrl_polarity_v2(active_pol); return gspi_csctrl_polarity_v1(active_pol); diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 376a40d3cf9a..8ab835e577fa 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -23,7 +23,7 @@ #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB) static void codecs_init(uint8_t *base, u32 codec_mask) { int i; @@ -65,7 +65,7 @@ static struct device_operations hda_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB) .init = hda_init, #endif .ops_pci = &pci_dev_ops_pci, diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 35f89c9021ba..0ad3e5c32a80 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -76,7 +76,7 @@ #define PAD_CFG1_PULL_UP_20K (0xc << 10) #define PAD_CFG1_PULL_UP_667 (0xd << 10) #define PAD_CFG1_PULL_NATIVE (0xf << 10) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) /* Tx enabled driving last value driven, Rx enabled */ #define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 14) /* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller @@ -125,7 +125,7 @@ #define PAD_CFG2_DEBOUNCE_MASK 0x1f /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) #define PAD_CFG1_TOL_MASK (0x1 << 25) #define PAD_CFG1_TOL_1V8 (0x1 << 25) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */ @@ -134,7 +134,7 @@ #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value #else @@ -147,7 +147,7 @@ PAD_CFG0_TRIG_##trig | \ PAD_CFG0_RX_POL_##inv) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ (PAD_CFG0_ROUTE_##route1 | \ PAD_CFG0_ROUTE_##route2 | \ @@ -180,7 +180,7 @@ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ PAD_IOSSTATE(TxLASTRxE)) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS */ @@ -269,7 +269,7 @@ */ #define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) #define PAD_CFG_GPI_APIC(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ @@ -384,7 +384,7 @@ PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 494a1b0fedf5..b3836377363b 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -240,7 +240,7 @@ void lpc_io_setup_comm_a_b(void) uint16_t com_enable = LPC_IOE_COMA_EN; /* ComB Range 2F8h-2FFh [6:4] */ - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) { com_ranges |= LPC_IOD_COMB_RANGE; com_enable |= LPC_IOE_COMB_EN; } diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index c191ad06cd89..0a5e1bf4d636 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -46,7 +46,7 @@ static void pch_pcie_init(struct device *dev) /* disable parity error response, enable ISA */ pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2); - if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) { + if (CONFIG(PCIE_DEBUG_INFO)) { printk(BIOS_SPEW, " MBL = 0x%08x\n", pci_read_config32(dev, PCI_MEMORY_BASE)); printk(BIOS_SPEW, " PMBL = 0x%08x\n", diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 61991c2f55ce..4a35a03ff186 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -25,7 +25,7 @@ #error "PCR_BASE_ADDRESS need to be non-zero!" #endif -#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) +#if !CONFIG(PCR_COMMON_IOSF_1_0) #define PCR_SBI_CMD_TIMEOUT 10 /* 10ms */ @@ -76,7 +76,7 @@ static void *__pcr_reg_address(uint8_t pid, uint16_t offset) void *pcr_reg_address(uint8_t pid, uint16_t offset) { - if (IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)) + if (CONFIG(PCR_COMMON_IOSF_1_0)) assert(IS_ALIGNED(offset, sizeof(uint32_t))); return __pcr_reg_address(pid, offset); @@ -91,7 +91,7 @@ void *pcr_reg_address(uint8_t pid, uint16_t offset) */ static inline void check_pcr_offset_align(uint16_t offset, size_t size) { - const size_t align = IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) ? + const size_t align = CONFIG(PCR_COMMON_IOSF_1_0) ? sizeof(uint32_t) : size; assert(IS_ALIGNED(offset, align)); @@ -219,7 +219,7 @@ void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata) pcr_write8(pid, offset, data8); } -#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) +#if !CONFIG(PCR_COMMON_IOSF_1_0) #ifdef __SIMPLE_DEVICE__ static int pcr_wait_for_completion(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1f25d756f3d8..43543a1cc509 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -66,7 +66,7 @@ static void pch_pmc_add_io_resources(struct device *dev, cfg->abase_addr, cfg->abase_size, IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED); - if (IS_ENABLED(CONFIG_PMC_INVALID_READ_AFTER_WRITE)) { + if (CONFIG(PMC_INVALID_READ_AFTER_WRITE)) { /* * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've * observed cases where the BAR reads back as 0, but the IO @@ -105,7 +105,7 @@ static void pch_pmc_read_resources(struct device *dev) void pmc_set_acpi_mode(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 6c967adfb00c..f58d36246e08 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -384,7 +384,7 @@ static int pmc_prev_sleep_state(const struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: @@ -432,7 +432,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps) return ps->prev_sleep_state; } -#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK) +#if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK) /* * If possible, lock 0xcf9. Once the register is locked, it can't be changed. * This lock is reset on cold boot, hard reset, soft reset and Sx. diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index 2d70de273b41..5a0d45cc0fce 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -53,7 +53,7 @@ void rtc_conf_set_bios_interface_lockdown(void) PCR_RTC_CONF_BILD); } -#if IS_ENABLED(CONFIG_INTEL_HAS_TOP_SWAP) +#if CONFIG(INTEL_HAS_TOP_SWAP) void configure_rtc_buc_top_swap(enum ts_config ts_state) { pcr_rmw32(PID_RTC, PCR_RTC_BUC, ~PCR_RTC_BUC_TOP_SWAP, ts_state); diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 4c32520123ac..0801cb77c4b0 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -52,7 +52,7 @@ static void sata_final(struct device *dev) /* Read Ports Implemented (GHC_PI) */ port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); - if (IS_ENABLED(CONFIG_SOC_AHCI_PORT_IMPLEMENTED_INVERT)) + if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) port_impl = ~port_impl; port_impl &= 0x07; /* bit 0-2 */ diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index ea8d1b02bcb4..2794a3b82e83 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -19,7 +19,7 @@ #include <device/pci_ids.h> #include <intelblocks/sd.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void sd_fill_ssdt(struct device *dev) { const char *path; @@ -59,7 +59,7 @@ static struct device_operations dev_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = sd_fill_ssdt, #endif .ops_pci = &pci_dev_ops_pci, diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index f1a2ca087438..1a215eb69d9c 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -133,7 +133,7 @@ static void tco_enable_bar(void) */ void tco_configure(void) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)) tco_enable_bar(); tco_timer_disable(); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0c10d6be49c1..16bb3a2d1da9 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -192,7 +192,7 @@ void smihandler_southbridge_sleep( mainboard_smi_sleep(slp_typ); /* Log S3, S4, and S5 entry */ - if (slp_typ >= ACPI_S3 && IS_ENABLED(CONFIG_ELOG_GSMI)) + if (slp_typ >= ACPI_S3 && CONFIG(ELOG_GSMI)) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Clear pending GPE events */ @@ -324,7 +324,7 @@ static void finalize(void) } finalize_done = 1; - if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ fast_spi_init(); @@ -361,13 +361,13 @@ void smihandler_southbridge_apmc( break; case APM_CNT_ACPI_DISABLE: pmc_disable_pm1_control(SCI_EN); - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) pmc_enable_smi(ESPI_SMI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: pmc_enable_pm1_control(SCI_EN); - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) pmc_disable_smi(ESPI_SMI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; @@ -387,11 +387,11 @@ void smihandler_southbridge_apmc( } break; case APM_CNT_ELOG_GSMI: - if (IS_ENABLED(CONFIG_ELOG_GSMI)) + if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(save_state_ops); break; case APM_CNT_SMMSTORE: - if (IS_ENABLED(CONFIG_SMMSTORE)) + if (CONFIG(SMMSTORE)) southbridge_smi_store(save_state_ops); break; case APM_CNT_FINALIZE: @@ -414,7 +414,7 @@ void smihandler_southbridge_pm1( */ if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) { /* power button pressed */ - if (IS_ENABLED(CONFIG_ELOG_GSMI)) + if (CONFIG(ELOG_GSMI)) elog_add_event(ELOG_TYPE_POWER_BUTTON); pmc_disable_pm1_control(-1UL); pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index d9299751861d..dd8bab34839a 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -95,7 +95,7 @@ void smm_region_info(void **start, size_t *size) *size = sa_get_tseg_size(); } -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS) static void smm_disable_espi(void *dest) { pmc_disable_smi(ESPI_SMI_EN); diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index c02cfed6a9c4..85db5cfa4a1c 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -26,7 +26,7 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, -#if !ENV_SMM && IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) +#if !ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI) { .ctrlr = &gspi_ctrlr, .bus_start = 1, .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)}, #endif diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index f9782aaa3818..d95a4ebedb58 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -160,7 +160,7 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) uintptr_t top_of_ram; int index = *resource_count; - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) dpr_size = sa_get_dpr_size(); /* Get SoC reserve memory size as per user selection */ @@ -270,7 +270,7 @@ static void systemagent_read_resources(struct device *dev) soc_add_fixed_mmio_resources(dev, &index); /* Calculate and add DRAM resources. */ sa_add_dram_resources(dev, &index); - if (IS_ENABLED(CONFIG_SA_ENABLE_IMR)) + if (CONFIG(SA_ENABLE_IMR)) /* Add the isolated memory ranges (IMRs). */ sa_add_imr_resources(dev, &index); } @@ -292,7 +292,7 @@ static struct device_operations systemagent_ops = { .enable_resources = pci_dev_enable_resources, .init = soc_systemagent_init, .ops_pci = &pci_dev_ops_pci, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = sa_write_acpi_tables, #endif }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7f105d7e1746..7f213722de9f 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -45,7 +45,7 @@ static void uart_lpss_init(uintptr_t baseaddr) CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); } -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) +#if CONFIG(DRIVERS_UART_8250MEM) uintptr_t uart_platform_base(int idx) { /* return Base address for UART console index */ @@ -92,7 +92,7 @@ struct device *uart_get_device(void) * config option is not selected. * By default return NULL in this case to avoid compilation errors. */ - if (!IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) return NULL; int console_index = uart_get_valid_index(); @@ -141,7 +141,7 @@ void uart_bootblock_init(void) uart_common_init(uart_get_device(), UART_BASE(CONFIG_UART_FOR_CONSOLE)); - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) + if (!CONFIG(DRIVERS_UART_8250MEM_32)) /* Put UART in byte access mode for 16550 compatibility */ soc_uart_set_legacy_mode(); @@ -156,7 +156,7 @@ static void uart_read_resources(struct device *dev) pci_dev_read_resources(dev); /* Set the configured UART base address for the debug port */ - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE) && + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) && uart_is_debug_controller(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); /* Need to set the base and size for the resource allocator. */ @@ -204,7 +204,7 @@ static bool uart_controller_needs_init(struct device *dev) * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing * controller here. */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) return false; /* If this device does not correspond to debug port, then skip. */ diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index f1bb93551eb1..c429e7dd5898 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -29,7 +29,7 @@ static struct device_operations usb_xhci_ops = { .init = soc_xhci_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_usb_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, #endif }; diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 8ccea5d6a1bb..6f79466b1055 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -58,7 +58,7 @@ static void dmi_lockdown_cfg(void) static void fast_spi_lockdown_cfg(int chipset_lockdown) { - if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI)) + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI)) return; /* Set FAST_SPI opcode menu */ diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 0bc30390641c..60fe0d861edb 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -22,7 +22,7 @@ void *vbt_get(void) { - if (!IS_ENABLED(CONFIG_RUN_FSP_GOP)) + if (!CONFIG(RUN_FSP_GOP)) return NULL; /* Normal mode and S3 resume path PEIM GFX init is not needed. diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 763363795069..f3e91ff451d7 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -83,7 +83,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = top_of_32bit_ram(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif @@ -140,7 +140,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) u16 pmbase = get_pmbase(); /* System Management */ - if (!IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (!CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = 0x00; fadt->acpi_enable = 0x00; fadt->acpi_disable = 0x00; diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 110d67d6deb8..f16ee20620f2 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -58,13 +58,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { -#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) +#if (CONFIG(CONSOLE_SERIAL)) early_uart_init(); #endif }; void bootblock_soc_init(void) { - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); }; diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index 955bf4b936b2..baa0878f5e7c 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -41,7 +41,7 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func, reg16 = pci_read_config16(uart_dev, PCI_BASE_ADDRESS_0) | mmio_base; pci_write_config16(uart_dev, PCI_BASE_ADDRESS_0, reg16); -#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE)) +#if (CONFIG(NON_LEGACY_UART_MODE)) /* Decode MMIO at MEMBA (BAR1) */ pci_write_config32(uart_dev, PCI_BASE_ADDRESS_1, CONFIG_CONSOLE_UART_BASE_ADDRESS + @@ -53,12 +53,12 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func, */ pci_write_config16(uart_dev, PCI_COMMAND, pci_read_config16(uart_dev, PCI_COMMAND) | -#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE)) +#if (CONFIG(NON_LEGACY_UART_MODE)) PCI_COMMAND_MEMORY | #endif PCI_COMMAND_MASTER | PCI_COMMAND_IO); -#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_230400)) +#if (CONFIG(CONSOLE_SERIAL_230400)) /* Change the highest speed to 230400 */ uint32_t *psr_reg = (uint32_t *)(CONFIG_CONSOLE_UART_BASE_ADDRESS + diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 29bea2b60f1c..68bd60c83a9e 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -50,7 +50,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = denverton_init_cpus, .scan_bus = NULL, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c index c70c22ad987c..e4aa78f29149 100644 --- a/src/soc/intel/denverton_ns/hob_mem.c +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -44,7 +44,7 @@ void soc_save_dimm_info(void) return; /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ - if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + if (CONFIG(DISPLAY_HOBS)) soc_display_fsp_smbios_memory_info_hob(memory_info_hob); /* diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index f5df21a792ad..af840a2f1a94 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -264,7 +264,7 @@ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index c9377092554b..25d7c9d3906d 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -210,7 +210,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -310,7 +310,7 @@ void southcluster_enable_dev(struct device *dev) static struct device_operations device_ops = { .read_resources = lpc_read_resources, .set_resources = pci_dev_set_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .write_acpi_tables = southcluster_write_acpi_tables, #endif diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 7d623dabf4d1..514d86d5b50c 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -51,7 +51,7 @@ u32 top_of_32bit_ram(void) /* * Add IQAT region size if enabled. */ -#if IS_ENABLED(CONFIG_IQAT_ENABLE) +#if CONFIG(IQAT_ENABLE) iqat_region_size = CONFIG_IQAT_MEMORY_REGION_SIZE; #endif return system_agent_region_base(TOLUD) - diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 193e41c2fc33..8b520873e5b6 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -38,7 +38,7 @@ static void pch_power_options(struct device *dev) { /* TODO */ } static void pch_set_acpi_mode(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 77364b80d283..4477c927e957 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -34,7 +34,7 @@ void __weak mainboard_config_gpios(void) {} -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +#if CONFIG(DISPLAY_HOBS) static void display_fsp_smbios_memory_info_hob(void) { const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; @@ -141,7 +141,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; uintptr_t top_of_ram; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -157,7 +157,7 @@ asmlinkage void car_stage_entry(void) fsp_memory_init(false); -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +#if CONFIG(DISPLAY_HOBS) display_fsp_smbios_memory_info_hob(); #endif @@ -176,7 +176,7 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -200,7 +200,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) BL_HSIO_INFORMATION *hsio_config; /* Set the parameters for MemoryInit */ - m_cfg->PcdEnableIQAT = IS_ENABLED(CONFIG_IQAT_ENABLE); + m_cfg->PcdEnableIQAT = CONFIG(IQAT_ENABLE); /* if ME HECI communication is disabled, apply default one*/ if (mupd->FspmConfig.PcdMeHeciCommunication == 0) { diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 9961778321d9..4d748b2a71e0 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -209,7 +209,7 @@ static void finalize(void) } finalize_done = 1; - if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ fast_spi_init(); } diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index ac779d050dcc..07e07045f51e 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -34,7 +34,7 @@ static void dnv_ns_uart_read_resources(struct device *dev) { /* read resources to be visible in the log*/ pci_dev_read_resources(dev); - if (!IS_ENABLED(CONFIG_LEGACY_UART_MODE)) + if (!CONFIG(LEGACY_UART_MODE)) return; struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res == NULL) @@ -88,6 +88,6 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) { if (phase != END_OF_FIRMWARE) return; - if (IS_ENABLED(CONFIG_LEGACY_UART_MODE)) + if (CONFIG(LEGACY_UART_MODE)) hide_hsuarts(); } diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 9701a338eb66..371581b77afd 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -89,7 +89,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl index ae958c2f010f..8e47f5c7a04c 100644 --- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl +++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl @@ -16,7 +16,7 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) // Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) Name(\_S3, Package(){0x5,0x5,0x0,0x0}) #endif Name(\_S4, Package(){0x6,0x6,0x0,0x0}) diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 89ea4c2adab8..15dc851b96cb 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -150,7 +150,7 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void enable_smis(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + if (CONFIG(HAVE_SMI_HANDLER)) southcluster_smm_enable_smi(); } diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 3786c0cc35df..c9cbcfe96013 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -307,7 +307,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 282083aa557d..8d4e090a405f 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -207,7 +207,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, } } -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) southcluster_smm_save_gpio_route(route_reg); #endif } diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index b28b195c87b2..75daba540e8a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -283,7 +283,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index ce66df8a6a15..9cbc95c240f7 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -39,7 +39,7 @@ void early_mainboard_romstage_entry(void); void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask, uint32_t *mask2); -#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1) +#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); #else static inline void byt_config_com1_and_enable(void) { } diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 62cc189b60b5..b4eb006aab22 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -63,7 +63,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear) if (pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S4: @@ -229,7 +229,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index ee0929d83dd7..f2abd9975a84 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -111,7 +111,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -207,7 +207,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -274,7 +274,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -293,7 +293,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 8fce928a2da3..e6947b4d6d2e 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -139,7 +139,7 @@ static void sc_enable_serial_irqs(struct device *dev) write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) /* * SoC requires that the System BIOS first set the SERIRQ logic to * continuous mode operation for at least one frame before switching diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4bc924c50059..573c1c439055 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -138,7 +138,7 @@ enum { static uint8_t readb_(const void *addr) { uint8_t v = read8(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", v, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -148,7 +148,7 @@ static uint8_t readb_(const void *addr) static uint16_t readw_(const void *addr) { uint16_t v = read16(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", v, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -158,7 +158,7 @@ static uint16_t readw_(const void *addr) static uint32_t readl_(const void *addr) { uint32_t v = read32(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", v, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -168,7 +168,7 @@ static uint32_t readl_(const void *addr) static void writeb_(uint8_t b, void *addr) { write8(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", b, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -177,7 +177,7 @@ static void writeb_(uint8_t b, void *addr) static void writew_(uint16_t b, void *addr) { write16(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", b, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -186,7 +186,7 @@ static void writew_(uint16_t b, void *addr) static void writel_(uint32_t b, void *addr) { write32(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", b, (((uint32_t) addr) & SPI_OFFSET_MASK)); } diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index f6dd2a7021d4..348e1c00f1a7 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -30,7 +30,7 @@ static void pci_domain_set_resources(struct device *dev) assign_resources(dev->link_list); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *domain_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -45,7 +45,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = domain_acpi_name #endif }; diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index b8ef6b18b453..54e796d48d98 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -51,22 +51,22 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Serial Port */ - if (IS_ENABLED(CONFIG_INTEGRATED_UART)) { + if (CONFIG(INTEGRATED_UART)) { UpdData->SerialPortConfigure = 1; /* values are from FSP .bsf file */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_9600)) + if (CONFIG(CONSOLE_SERIAL_9600)) UpdData->SerialPortBaudRate = 8; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_19200)) + else if (CONFIG(CONSOLE_SERIAL_19200)) UpdData->SerialPortBaudRate = 9; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_38400)) + else if (CONFIG(CONSOLE_SERIAL_38400)) UpdData->SerialPortBaudRate = 10; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_57600)) + else if (CONFIG(CONSOLE_SERIAL_57600)) UpdData->SerialPortBaudRate = 11; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_115200)) + else if (CONFIG(CONSOLE_SERIAL_115200)) UpdData->SerialPortBaudRate = 12; } - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) UpdData->SerialPortType = 0; UpdData->DebugOutputLevel = CONFIG_FSP_DEBUG_LEVEL; @@ -74,19 +74,19 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Memory Down */ - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN)) { + if (CONFIG(FSP_MEMORY_DOWN)) { UpdData->MemDownEnable = 1; - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) UpdData->MemDownCh0Dimm0SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) UpdData->MemDownCh0Dimm1SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) UpdData->MemDownCh1Dimm0SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) UpdData->MemDownCh1Dimm1SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_SPD, NULL); } else { @@ -98,7 +98,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Fast Boot */ - if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) + if (CONFIG(ENABLE_MRC_CACHE)) UpdData->MemFastBoot = 1; else UpdData->MemFastBoot = 0; @@ -106,18 +106,18 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Hyper-Threading */ - if (IS_ENABLED(CONFIG_FSP_HYPERTHREADING)) + if (CONFIG(FSP_HYPERTHREADING)) UpdData->HyperThreading = 1; else UpdData->HyperThreading = 0; /* Enable USB */ - if (IS_ENABLED(CONFIG_FSP_EHCI1_ENABLE)) + if (CONFIG(FSP_EHCI1_ENABLE)) UpdData->Ehci1Enable = 1; else UpdData->Ehci1Enable = 0; - if (IS_ENABLED(CONFIG_FSP_EHCI2_ENABLE)) + if (CONFIG(FSP_EHCI2_ENABLE)) UpdData->Ehci2Enable = 1; else UpdData->Ehci2Enable = 0; @@ -133,7 +133,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fs ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 80795c303e32..32429ae2365b 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -61,7 +61,7 @@ static void setup_gpio_io_address(void) void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); - if (!IS_ENABLED(CONFIG_INTEGRATED_UART)) { + if (!CONFIG(INTEGRATED_UART)) { /* Enable decoding of I/O locations for Super I/O devices */ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); @@ -105,7 +105,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 5c0cb7e5abce..5b90bbbdd181 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -228,7 +228,7 @@ static void sc_init(struct device *dev) /* Program Serial IRQ register. */ pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_CONT); - if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) { + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) { /* If SERIRQ have to operate in quiet mode, it should have been run in continuous mode for at least one frame first. Use I/O access to achieve the delay of at least one LPC cycle. */ @@ -263,7 +263,7 @@ void southcluster_enable_dev(struct device *dev) } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *lpc_acpi_name(const struct device *dev) { if (dev->path.pci.devfn == LPC_DEV_FUNC) @@ -281,7 +281,7 @@ static struct device_operations device_ops = { .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, #endif }; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 967fe284bda0..1ad89600c1bf 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -202,14 +202,14 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) /* Update the mem console pointer. */ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; } else diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index d26fa4210d8e..b76dc4ba37f3 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -32,7 +32,7 @@ void bootblock_soc_early_init(void) bootblock_pch_early_init(); bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } diff --git a/src/soc/intel/icelake/bootblock/cpu.c b/src/soc/intel/icelake/bootblock/cpu.c index f02b09027ac8..e23286c2d209 100644 --- a/src/soc/intel/icelake/bootblock/cpu.c +++ b/src/soc/intel/icelake/bootblock/cpu.c @@ -20,7 +20,7 @@ void bootblock_cpu_init(void) { /* Temporarily cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && - IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && + CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index ff4d96607969..2d35f5bf39ca 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -139,7 +139,7 @@ void pch_early_iorange_init(void) LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 0fb0b0ecec52..0978ab3dead7 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -30,7 +30,7 @@ #include <soc/ramstage.h> #include <string.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -129,7 +129,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, - #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index f0ad0e25a09c..1539b4210837 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -54,7 +54,7 @@ void graphics_soc_init(struct device *dev) * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) + if (CONFIG(INTEL_GMA_ADD_VBT)) return; /* IGD needs to Bus Master */ diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index a9cd748b0cf9..f556b115144e 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -49,7 +49,7 @@ struct smm_relocation_params { /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/lpc.c index e1958651436d..a3bce93a7dd4 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/lpc.c @@ -220,7 +220,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else lpc_set_serirq_mode(SERIRQ_QUIET); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index faf1b2a6c354..821162e768ef 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -146,7 +146,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, traditional_mem_base -= sa_get_tseg_size(); /* Get DPR size */ - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) traditional_mem_base -= sa_get_dpr_size(); /* Traditional Area Size */ diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 0c35d722fae6..ddf642003f0a 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -91,7 +91,7 @@ void smihandler_soc_at_finalize(void) void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index d3aa900214f5..ff5b9b2a52eb 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -79,7 +79,7 @@ static const struct reg_script mtrr_init[] = { asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) + if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) light_sd_led(); bootblock_main_with_timestamp(base_timestamp, NULL, 0); @@ -87,7 +87,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY)) + if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY)) light_sd_led(); /* Initialize the MTRRs */ @@ -98,18 +98,18 @@ void bootblock_soc_early_init(void) reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); /* Enable the HSUART */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + if (CONFIG(ENABLE_BUILTIN_HSUART0)) reg_script_run_on_dev(HSUART0_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + if (CONFIG(ENABLE_BUILTIN_HSUART1)) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT)) + if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT)) light_sd_led(); } void bootblock_soc_init(void) { - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY)) + if (CONFIG(ENABLE_DEBUG_LED_SOC_INIT_ENTRY)) light_sd_led(); display_mtrrs(); diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index 67d223817ddc..13a4d63d3c50 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -459,7 +459,7 @@ stackless_PCIConfig_Read: esram_init_done: -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) +#if CONFIG(ENABLE_DEBUG_LED) sd_led: /* Set the SDIO controller's base address */ @@ -491,7 +491,7 @@ L43: jmp stackless_PCIConfig_Read L44: -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM) +#if CONFIG(ENABLE_DEBUG_LED_ESRAM) jmp light_sd_led #endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */ #endif /* CONFIG_ENABLE_DEBUG_LED */ diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index a3bfb3bcbb9d..595c818593b2 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -67,7 +67,7 @@ static int platform_i2c_write(uint32_t restart, uint8_t *tx_buffer, int length, if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C write error!\n", status); @@ -76,7 +76,7 @@ static int platform_i2c_write(uint32_t restart, uint8_t *tx_buffer, int length, /* Check for timeout */ if (stopwatch_expired(timeout)) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C write timeout!\n", status); @@ -142,7 +142,7 @@ static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length, if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C read error!\n", status); @@ -151,7 +151,7 @@ static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length, /* Check for timeout */ if (stopwatch_expired(timeout)) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C read timeout!\n", status); @@ -204,7 +204,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, uint8_t *tx_buffer; int tx_bytes; - if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + if (CONFIG(I2C_DEBUG)) { for (index = 0; index < seg_count;) { if (index == 0) printk(BIOS_ERR, "I2C Start\n"); @@ -283,7 +283,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, /* Return any detected error */ if (data_bytes < 0) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "I2C segment[%d] failed\n", index); @@ -299,7 +299,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, /* Return any detected error */ if (data_bytes < 0) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "I2C segment[%d] failed\n", index); @@ -330,7 +330,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); - if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + if (CONFIG(I2C_DEBUG)) { printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C read error!\n", status); @@ -343,7 +343,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, /* Check for timeout */ if (stopwatch_expired(&timeout)) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + if (CONFIG(I2C_DEBUG)) { printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C read timeout!\n", status); @@ -362,7 +362,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, regs->ic_tar = 0; /* Return the number of bytes transferred */ - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: bytes transferred\n", bytes_transferred); return bytes_transferred; diff --git a/src/soc/intel/quark/romstage/car.c b/src/soc/intel/quark/romstage/car.c index 9f052a31ec4c..8ad87d2f4369 100644 --- a/src/soc/intel/quark/romstage/car.c +++ b/src/soc/intel/quark/romstage/car.c @@ -54,9 +54,9 @@ void car_soc_pre_console_init(void) reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); /* Enable the HSUART */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + if (CONFIG(ENABLE_BUILTIN_HSUART0)) reg_script_run_on_dev(HSUART0_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + if (CONFIG(ENABLE_BUILTIN_HSUART1)) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index b8207117fa4d..d51587143b96 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,7 +29,7 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" #endif @@ -57,7 +57,7 @@ car_stage_entry: .Lhlt: xchg %al, %ah mov $POST_DELAY, %dh -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb %al, $CONFIG_POST_IO_PORT #else post_code(POST_DEAD_CODE) @@ -67,7 +67,7 @@ car_stage_entry: .flash_delay: outb %al, $0xED loop .flash_delay -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) +#if CONFIG(ENABLE_DEBUG_LED) movl $SD_HOST_CTRL, %ebx movb 0(%ebx), %dl xorb $1, %dl diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index c237da5270ba..31e130a39853 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -36,7 +36,7 @@ asmlinkage void *car_stage_c_entry(void) post_code(0x20); console_init(); - if (IS_ENABLED(CONFIG_STORAGE_TEST)) { + if (CONFIG(STORAGE_TEST)) { uint32_t bar; pci_devfn_t dev; uint32_t previous_bar; @@ -132,7 +132,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; /* Display the ESRAM layout */ - if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) { + if (CONFIG(DISPLAY_ESRAM_LAYOUT)) { printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); printk(BIOS_SPEW, "+-------------------+ 0x80080000 - ESRAM end\n"); @@ -175,7 +175,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) upd->RmuLength = rmu_data_len; upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW) ? (uintptr_t)fsp_write_line : 0; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->SmmTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal; upd->SocWrRonVal = config->SocWrRonVal; diff --git a/src/soc/intel/quark/sd.c b/src/soc/intel/quark/sd.c index c10ac4fbf1e0..08db791ffd00 100644 --- a/src/soc/intel/quark/sd.c +++ b/src/soc/intel/quark/sd.c @@ -23,7 +23,7 @@ static void init(struct device *dev) { /* Run the SD test */ - if (IS_ENABLED(CONFIG_STORAGE_TEST)) { + if (CONFIG(STORAGE_TEST)) { uint32_t bar; uint32_t previous_bar; uint16_t previous_command; diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 36819a4700f2..79901f29ff04 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -27,7 +27,7 @@ #include <soc/storage_test.h> #include <string.h> -#if IS_ENABLED(CONFIG_STORAGE_LOG) +#if CONFIG(STORAGE_LOG) struct log_entry log[LOG_ENTRIES] CAR_GLOBAL; uint8_t log_index CAR_GLOBAL; int log_full CAR_GLOBAL; @@ -37,7 +37,7 @@ long log_start_time CAR_GLOBAL; static uint8_t drivers_storage[256] CAR_GLOBAL; #define STORAGE_DEBUG BIOS_DEBUG -#define LOG_DEBUG (IS_ENABLED(CONFIG_STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER) +#define LOG_DEBUG (CONFIG(STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER) #ifdef __SIMPLE_DEVICE__ uint32_t storage_test_init(pci_devfn_t dev, uint32_t *previous_bar, @@ -88,7 +88,7 @@ void storage_test_complete(struct device *dev, uint32_t previous_bar, static void display_log(void) { /* Determine the array bounds */ - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { long delta; uint8_t end; uint8_t index; @@ -121,7 +121,7 @@ static void display_log(void) void sdhc_log_command(struct mmc_command *cmd) { - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { timer_monotonic_get(&log[log_index].time); log[log_index].cmd = *cmd; log[log_index].cmd_issued = 0; @@ -133,7 +133,7 @@ void sdhc_log_command(struct mmc_command *cmd) void sdhc_log_command_issued(void) { - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { log[log_index].cmd_issued = 1; } } @@ -142,7 +142,7 @@ void sdhc_log_response(uint32_t entries, uint32_t *response) { unsigned int entry; - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { log[log_index].response_entries = entries; for (entry = 0; entry < entries; entry++) log[log_index].response[entry] = response[entry]; @@ -151,7 +151,7 @@ void sdhc_log_response(uint32_t entries, uint32_t *response) void sdhc_log_ret(int ret) { - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { log[log_index].ret = ret; if (++log_index == 0) log_full = 1; @@ -189,7 +189,7 @@ void storage_test(uint32_t bar, int full_initialization) storage_display_setup(media); } else { /* Initialize the log */ - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { log_index = 0; log_full = 0; } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 53e6b3c0a8e6..26a131ddc26a 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -182,15 +182,15 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif @@ -207,7 +207,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); } @@ -275,7 +275,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->mon_alrm = 0x00; fadt->century = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; - if (!IS_ENABLED(CONFIG_NO_FADT_8042)) + if (!CONFIG(NO_FADT_8042)) fadt->iapc_boot_arch |= ACPI_FADT_8042; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index ebf4289218e6..8788bd3e9345 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -78,7 +78,7 @@ Device (GPIO) */ Method (GADD, 1, NotSerialized) { -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) /* GPIO Community 0 */ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) { diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0c4decc186d0..0aba2e7542ec 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -74,6 +74,6 @@ Method (_OSC, 4) } /* SGX */ -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> #endif diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index e766fd767f86..ad68ef90cfbb 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -112,7 +112,7 @@ Device (EMMC) } } -#if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE) +#if !CONFIG(EXCLUDE_NATIVE_SD_INTERFACE) Device (SDXC) { Name (_ADR, 0x001E0006) diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index acf25ffd48a1..4358fba40f38 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -32,14 +32,14 @@ void bootblock_soc_early_init(void) bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } void bootblock_soc_init(void) { /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + if (CONFIG(PLATFORM_USES_FSP1_1)) bootblock_fsp_temp_ram_init(); /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 34cc71312482..0f6c8a85d438 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -71,7 +71,7 @@ static void soc_config_acpibase(void) */ reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); else pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0); @@ -105,7 +105,7 @@ static void soc_config_pwrmbase(void) pcr_write32(PID_DMI, PCR_DMI_PMBASEA, ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16))); - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8); else pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0); @@ -131,7 +131,7 @@ void pch_early_iorange_init(void) LPC_IOE_EC_62_66; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1f32a3efa263..98e5baf483fa 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -60,7 +60,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif @@ -68,7 +68,7 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .init = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e43aa833f4a1..15eb6b26518a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -194,7 +194,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif @@ -205,7 +205,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif }; @@ -323,7 +323,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; - params->CpuConfig.Bits.VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); + params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX); params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 910dcb88c90b..0ff5a137c6fa 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -489,7 +489,7 @@ static void post_mp_init(void) smm_southbridge_enable(GBL_EN); /* Lock down the SMRAM space. */ -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) smm_lock(); #endif diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 4da705da73d2..3d66fa460200 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -41,7 +41,7 @@ static const struct pad_group skl_community_com0_groups[] = { static const struct pad_group skl_community_com1_groups[] = { INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */ -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ INTEL_GPP(GPP_C0, GPP_F0, GPP_F23), /* GPP F */ @@ -54,7 +54,7 @@ static const struct pad_group skl_community_com1_groups[] = { }; static const struct pad_group skl_community_com3_groups[] = { -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ #else INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ @@ -86,7 +86,7 @@ static const struct pad_community skl_gpio_communities[] = { }, { .port = PID_GPIOCOM1, .first_pad = GPP_C0, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) .last_pad = GPP_H23, #else .last_pad = GPP_E23, @@ -105,7 +105,7 @@ static const struct pad_community skl_gpio_communities[] = { .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) .first_pad = GPP_I0, .last_pad = GPP_I10, #else @@ -159,7 +159,7 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) { GPP_E, GPP_E}, { GPP_F, GPP_F}, { GPP_G, GPP_G}, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) { GPP_H, GPP_H}, { GPP_I, GPP_I}, #endif @@ -172,7 +172,7 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) return reg_val; /* * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 1bf6ba410cd3..07ee67ab88a3 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -59,9 +59,9 @@ void graphics_soc_init(struct device *dev) * In case of non-FSP solution, SoC need to select another * Kconfig to perform GFX initialization. */ - if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) { + if (CONFIG(RUN_FSP_GOP)) { /* nothing to do */ - } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { int lightup_ok; gma_gfxinit(&lightup_ok); @@ -101,7 +101,7 @@ uintptr_t graphics_soc_write_acpi_opregion(struct device *device, global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); /* If GOP is not used, exit here */ - if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) + if (!CONFIG(INTEL_GMA_ADD_VBT)) return current; /* If IGD is disabled, exit here */ diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index f5065148d39a..74328b217e87 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -18,7 +18,7 @@ #include <intelblocks/systemagent.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) #include <fsp/bootblock.h> #else static inline void bootblock_fsp_temp_ram_init(void) {} diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 137b37e61354..1c143a2c43c5 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -18,7 +18,7 @@ #ifndef __ACPI__ #include <stddef.h> #endif -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> #else # include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 24bc2a8c1d3a..615edac0978c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -173,7 +173,7 @@ struct chipset_power_state { * This is used only in FSP1_1 as we wanted to keep the flow unchanged. * Internally fill_power_state calls the new pmc_fill_power_state now */ -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) struct chipset_power_state *fill_power_state(void); #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 819544095210..72992d25174a 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,7 +48,7 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 064ec3118f37..465e24870014 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -19,7 +19,7 @@ #ifndef _SOC_VR_CONFIG_H_ #define _SOC_VR_CONFIG_H_ -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) #include <fsp/soc_binding.h> #else #include <fsp/api.h> @@ -69,7 +69,7 @@ struct vr_config { #define VR_CFG_AMP(i) ((i) * 4) -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 63ff18d4062b..f7aa584f372c 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -239,7 +239,7 @@ static void print_me_version(void *unused) * Print ME version only if UART debugging is enabled. Else, it takes ~1 * second to talk to ME and get this information. */ - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) return; hfs.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index bca151e52244..60a7070408fc 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -31,7 +31,7 @@ size_t mmap_region_granularity(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + if (CONFIG(HAVE_SMI_HANDLER)) /* Align to TSEG size when SMM is in use */ if (CONFIG_SMM_TSEG_SIZE != 0) return CONFIG_SMM_TSEG_SIZE; @@ -142,7 +142,7 @@ static size_t get_prmrr_size(uintptr_t dram_base, uintptr_t prmrr_base = dram_base; size_t prmrr_size; - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + if (CONFIG(PLATFORM_USES_FSP1_1)) prmrr_size = 1*MiB; else prmrr_size = config->PrmrrSize; @@ -186,7 +186,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, traditional_mem_base -= sa_get_tseg_size(); /* Get DPR size */ - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) traditional_mem_base -= sa_get_dpr_size(); /* Traditional Area Size */ diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index 948245692241..ee04f0272d3b 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -28,7 +28,7 @@ car_stage_entry: .Lhlt: xchg %al, %ah -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb %al, $CONFIG_POST_IO_PORT #else post_code(POST_DEAD_CODE) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index e147f0c0aa47..dc9c528c0667 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -88,7 +88,7 @@ void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index c1a0b97cb2ad..43ba9c9c6f0c 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -166,7 +166,7 @@ asmlinkage void car_stage_entry(void) top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { void *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -225,7 +225,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->RMT = config->Rmt; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) @@ -281,7 +281,7 @@ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index e402ba5e8d23..2e93075f7b8e 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -27,7 +27,7 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 89169d0e7c90..905154e8ac27 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -127,7 +127,7 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, }, -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) [VR_RING] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -240,7 +240,7 @@ void fill_vr_domain_config(void *params, vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) +#if CONFIG(PLATFORM_USES_FSP2_0) vr_params->AcLoadline[domain] = cfg->ac_loadline; vr_params->DcLoadline[domain] = cfg->dc_loadline; #endif diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 3f8e149727b9..2d998947bbf9 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -70,7 +70,7 @@ static struct mtk_i2c i2c[7] = { #define I2CTAG "[I2C][PL] " -#if IS_ENABLED(CONFIG_DEBUG_I2C) +#if CONFIG(DEBUG_I2C) #define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg) #else #define I2CLOG(fmt, arg...) diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h index 8d449f7950c9..041cfaa76fad 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h @@ -178,7 +178,7 @@ void dramk_check_dq_win(struct dqs_perbit_dly *p, u8 dly_step, u8 last_step, u32 void tx_delay_for_wrleveling(u32 channel, struct dqs_perbit_dly *dqdqs_perbit_dly, u8 *ave_dqdly_byte, u8 *max_dqsdly_byte); -#if IS_ENABLED(CONFIG_DEBUG_DRAM) +#if CONFIG(DEBUG_DRAM) #define dramc_dbg_msg(_x_...) printk(BIOS_DEBUG, _x_) #else #define dramc_dbg_msg(_x_...) diff --git a/src/soc/mediatek/mt8173/memory.c b/src/soc/mediatek/mt8173/memory.c index 066b18ba488b..f17f793cae5f 100644 --- a/src/soc/mediatek/mt8173/memory.c +++ b/src/soc/mediatek/mt8173/memory.c @@ -32,7 +32,7 @@ void mt_mem_init(const struct mt8173_sdram_params *sdram_params) /* memory calibration */ mt_set_emi(sdram_params); - if (IS_ENABLED(CONFIG_MEMORY_TEST)) { + if (CONFIG(MEMORY_TEST)) { /* * do memory test: * set memory scan range 0x2000 diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 65790d382300..2656d7252dfc 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -20,7 +20,7 @@ #include <soc/pmic_wrap.h> #include <types.h> -#if IS_ENABLED(CONFIG_DEBUG_PMIC) +#if CONFIG(DEBUG_PMIC) #define DEBUG_PMIC(level, x...) printk(level, x) #else #define DEBUG_PMIC(level, x...) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 04bb2bb28eb5..781443a397b4 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -21,7 +21,7 @@ #include <console/console.h> #define dramc_show(_x_...) printk(BIOS_INFO, _x_) -#if IS_ENABLED(CONFIG_DEBUG_DRAM) +#if CONFIG(DEBUG_DRAM) #define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_) #else #define dramc_dbg(_x_...) diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 5702b14a018d..b2c744198ba5 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -26,7 +26,7 @@ void mt_mem_init(const struct sdram_params *params) /* memory calibration */ mt_set_emi(params); - if (IS_ENABLED(CONFIG_MEMORY_TEST)) { + if (CONFIG(MEMORY_TEST)) { size_t r; u8 *addr = _dram; diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index cc1e284b668c..ce46e5ee3569 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -43,7 +43,7 @@ static void enable_cpu_power_partitions(void) power_ungate_partition(POWER_PARTID_C0NC); power_ungate_partition(POWER_PARTID_CE0); - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) { + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) { /* * Deassert reset signal of all the secondary CPUs. * PMC and flow controller will take over the power sequence diff --git a/src/soc/nvidia/tegra210/include/soc/console_uart.h b/src/soc/nvidia/tegra210/include/soc/console_uart.h index fc3048132662..e35b582fa206 100644 --- a/src/soc/nvidia/tegra210/include/soc/console_uart.h +++ b/src/soc/nvidia/tegra210/include/soc/console_uart.h @@ -29,19 +29,19 @@ enum console_uart_id { static inline enum console_uart_id console_uart_get_id(void) { - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTA)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTA)) return UART_ID_A; - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTB)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTB)) return UART_ID_B; - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTC)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTC)) return UART_ID_C; - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTD)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTD)) return UART_ID_D; - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTE)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTE)) return UART_ID_E; return UART_ID_NONE; diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h index ca369ad3cf59..df13cc4f7725 100644 --- a/src/soc/nvidia/tegra210/include/soc/mtc.h +++ b/src/soc/nvidia/tegra210/include/soc/mtc.h @@ -18,7 +18,7 @@ #include <boot/coreboot_tables.h> -#if IS_ENABLED(CONFIG_HAVE_MTC) +#if CONFIG(HAVE_MTC) int tegra210_run_mtc(void); void soc_add_mtc(struct lb_header *header); diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 213d69d6baff..bfa3c0afb413 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -43,7 +43,7 @@ void romstage(void) printk(BIOS_INFO, "T210: romstage here\n"); -#if IS_ENABLED(CONFIG_BOOTROM_SDRAM_INIT) +#if CONFIG(BOOTROM_SDRAM_INIT) printk(BIOS_INFO, "T210 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", sdram_get_ram_code()); #else diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index b8359987f98c..a9d6835b3a71 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -78,7 +78,7 @@ static void enable_tegra210_dev(struct device *dev) if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) return; if (display_init_required()) diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 90edd11cfbfb..eb3731b7f719 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -54,7 +54,7 @@ static const uart_params_t uart_board_param = { .blsp_uart = BLSP1_UART1, .dbg_uart_gpio = { { -#if IS_ENABLED(CONFIG_IPQ_QFN_PART) +#if CONFIG(IPQ_QFN_PART) .gpio = 60, .func = 2, #else /* bga */ @@ -66,7 +66,7 @@ static const uart_params_t uart_board_param = { .enable = GPIO_ENABLE }, { -#if IS_ENABLED(CONFIG_IPQ_QFN_PART) +#if CONFIG(IPQ_QFN_PART) .gpio = 61, .func = 2, #else /* bga */ diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index bb85acf8ccb1..fa0990b10b32 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -30,7 +30,7 @@ static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); - if (is_pmu_gpio(gpio) && IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288)) + if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288)) clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), pull_val << (gpio.idx * 2)); else diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index 2ac4bfcdce09..e4045a8937fe 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -67,7 +67,7 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns) { unsigned long period, duty; -#if IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288) +#if CONFIG(SOC_ROCKCHIP_RK3288) /*use rk pwm*/ write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0)); #endif diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 586eaf0d12bb..5252232f399a 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -660,7 +660,7 @@ void rkclk_configure_ddr(unsigned int hz) } rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg); - if (IS_ENABLED(CONFIG_RK3399_SPREAD_SPECTRUM_DDR)) + if (CONFIG(RK3399_SPREAD_SPECTRUM_DDR)) rkclk_set_dpllssc(&dpll_cfg); } diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 6e5e1a7f9656..65b791d5a3c0 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -49,7 +49,7 @@ static void soc_init(struct device *dev) */ mmio_resource(dev, 1, (TZRAM_BASE / KiB), (TZRAM_SIZE / KiB)); - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) rk_display_init(dev); else printk(BIOS_INFO, "Display initialization disabled.\n"); |