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-rw-r--r--src/southbridge/amd/cimx/sb900/SbPlatform.h4
-rw-r--r--src/southbridge/amd/cimx/sb900/cfg.c4
-rw-r--r--src/southbridge/amd/cimx/sb900/early.c10
-rw-r--r--src/southbridge/amd/cimx/sb900/late.c2
-rw-r--r--src/southbridge/amd/cimx/sb900/lpc.c6
-rw-r--r--src/southbridge/amd/cimx/sb900/smbus.c4
6 files changed, 15 insertions, 15 deletions
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 6371bcd69ee7..67c33e8f85cf 100644
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -70,7 +70,7 @@ typedef union _PCI_ADDR {
//------------------------------------------------------------------------------------------------------------------------//
/**
- * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
+ * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over
* SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
* SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
* HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
@@ -88,7 +88,7 @@ typedef union _PCI_ADDR {
* GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
* UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
* SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
- * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
+ * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11)
* SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
* SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
* SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c
index c596a372e308..5a8b2252bb02 100644
--- a/src/southbridge/amd/cimx/sb900/cfg.c
+++ b/src/southbridge/amd/cimx/sb900/cfg.c
@@ -26,7 +26,7 @@
/**
* @brief South Bridge CIMx configuration
*
- * should be called before exeucte CIMx function.
+ * should be called before execute CIMx function.
* this function will be called in romstage and ramstage.
*/
void sb900_cimx_config(AMDSBCFG *sb_config)
@@ -274,7 +274,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_config)
sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option
// sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired
sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option
- sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option
+ sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internal Option
sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level
sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level
sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 6e4e44e169ad..b6b4ce1e1756 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -74,7 +74,7 @@ void sb_poweron_init(void)
//AmdSbDispatcher(&sb_early_cfg);
//TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
- // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbPowerOnInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n");
}
@@ -93,7 +93,7 @@ void sb_before_pci_init(void)
//AmdSbDispatcher(&sb_early_cfg);
//TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
- // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbBeforePciInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n");
}
@@ -109,7 +109,7 @@ void sb_After_Pci_Init(void)
//AmdSbDispatcher(&sb_early_cfg);
//TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
- // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbAfterPciInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
#endif
@@ -125,7 +125,7 @@ void sb_Mid_Post_Init(void)
//AmdSbDispatcher(&sb_early_cfg);
//TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
- // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbMidPostInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n");
}
@@ -142,7 +142,7 @@ void sb_Late_Post(void)
//AmdSbDispatcher(&sb_early_cfg);
//TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
- // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ // VerifyImage() will fail, LocateImage() take minutes to find the image.
sbLatePost(&sb_early_cfg);
//Set ACPI SCI IRQ to 0x9.
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 00e9a27c1ca9..6f6a5010bb8b 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -29,7 +29,7 @@
#include <device/pci_ehci.h>
#include <arch/acpi.h>
#include "lpc.h" /* lpc_read_resources */
-#include "SbPlatform.h" /* Platfrom Specific Definitions */
+#include "SbPlatform.h" /* Platform Specific Definitions */
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
index ce1be11da7fa..e9b782fa95d6 100644
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
@@ -74,7 +74,7 @@ void lpc_set_resources(struct device *dev)
/**
* @brief Enable resources for children devices
*
- * @param dev the device whos children's resources are to be enabled
+ * @param dev the device whose children's resources are to be enabled
*
*/
void lpc_enable_childrens_resources(device_t dev)
@@ -116,13 +116,13 @@ void lpc_enable_childrens_resources(device_t dev)
case 0x2f8: /* COM2 */
reg |= (1 << 7);
break;
- case 0x378: /* Parallal 1 */
+ case 0x378: /* Parallel 1 */
reg |= (1 << 0);
break;
case 0x3f0: /* FD0 */
reg |= (1 << 26);
break;
- case 0x220: /* Aduio 0 */
+ case 0x220: /* Audio 0 */
reg |= (1 << 8);
break;
case 0x300: /* Midi 0 */
diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
index 1dbbe5abb190..01b6af983f4e 100644
--- a/src/southbridge/amd/cimx/sb900/smbus.c
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
@@ -205,7 +205,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
tmp |= val;
/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
- outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
+ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
outl(tmp, AB_DATA);
outl(0, AB_INDX);
printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - End.\n");
@@ -228,7 +228,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
tmp |= val;
//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
- outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
+ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
outl(tmp, AB_DATA);
outl(0, AB_INDX);
printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - End.\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 01:17:13 +0000