summaryrefslogtreecommitdiffstats
path: root/src/southbridge/amd/cimx
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/amd/cimx')
-rw-r--r--src/southbridge/amd/cimx/sb700/bootblock.c2
-rw-r--r--src/southbridge/amd/cimx/sb700/early.c2
-rw-r--r--src/southbridge/amd/cimx/sb700/sb_cimx.h2
-rw-r--r--src/southbridge/amd/cimx/sb800/SBPLATFORM.h2
-rw-r--r--src/southbridge/amd/cimx/sb800/cfg.c4
-rw-r--r--src/southbridge/amd/cimx/sb800/early.c4
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c4
-rw-r--r--src/southbridge/amd/cimx/sb800/sb_cimx.h2
-rw-r--r--src/southbridge/amd/cimx/sb900/bootblock.c2
9 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 401c03916576..ce7707bd07c9 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -22,7 +22,7 @@
#include <arch/romcc_io.h>
-#if CONFIG_CONSOLE_POST == 1
+#if CONFIG_CONSOLE_POST
/* Data */
#define UART_RBR 0x00
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index c899320c48f9..3f647c8847de 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -31,7 +31,7 @@
#include "smbus.h"
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h
index 632e4cdcd5a5..8e62048d2e17 100644
--- a/src/southbridge/amd/cimx/sb700/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h
@@ -40,7 +40,7 @@ void sb_Late_Post(void);
void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);
void sb7xx_51xx_disable_wideio(u8 wio_index);
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number, called by finalize_node_setup()
* @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 7dc752a6cb79..22d7724890d7 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -158,7 +158,7 @@ typedef union _PCI_ADDR {
#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
#include "spi.h"
#endif
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 2b7315559a34..71fea672d5b1 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -26,7 +26,7 @@
#include <arch/io.h>
#include <arch/acpi.h>
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int acpi_get_sleep_type(void)
{
u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
@@ -75,7 +75,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
if (!sb_config)
return;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
if (acpi_get_sleep_type() == 3)
sb_config->S3Resume = 1;
#endif
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index f692897dcc46..c0f85330f5c6 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -30,7 +30,7 @@
#include "cbmem.h"
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
@@ -82,7 +82,7 @@ void sb800_clk_output_48Mhz(void)
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int acpi_is_wakeup_early(void)
{
return (acpi_get_sleep_type() == 3);
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index c69782bc62d6..0ce82b330710 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -161,7 +161,7 @@ static const struct pci_driver raid5_driver __pci_driver = {
.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5,
};
-#if CONFIG_USBDEBUG == 1
+#if CONFIG_USBDEBUG
static void usb_set_resources(struct device *dev)
{
struct resource *res;
@@ -480,7 +480,7 @@ static void sb800_enable(device_t dev)
/* call the CIMX entry at the last sb800 device,
* so make sure the mainboard devicetree is complete
*/
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3)
sb_Before_Pci_Init();
else
diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h
index 5e510de5197f..9916c8139b6f 100644
--- a/src/southbridge/amd/cimx/sb800/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h
@@ -40,7 +40,7 @@ int acpi_is_wakeup_early(void);
*/
void sb800_clk_output_48Mhz(void);
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number, called by finalize_node_setup()
* @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index e84743bc208c..61c3c3e9286b 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -22,7 +22,7 @@
#include <arch/romcc_io.h>
-#if CONFIG_CONSOLE_POST == 1
+#if CONFIG_CONSOLE_POST
/* Data */
#define UART_RBR 0x00