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-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c2
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c6
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h4
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c6
4 files changed, 9 insertions, 9 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
index 68a2dcd40220..f067c03317f4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -132,7 +132,7 @@ PcieTopologyPrepareForReconfig (
}
-UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+CONST UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
/*----------------------------------------------------------------------------------------*/
/**
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
index 3911dbf356ec..ff425c5c1635 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -135,7 +135,7 @@ BOOLEAN
PcieUtilSearchArray (
IN UINT8 *Buf1,
IN UINTN Buf1Length,
- IN UINT8 *Buf2,
+ CONST IN UINT8 *Buf2,
IN UINTN Buf2Length
)
{
@@ -143,7 +143,7 @@ PcieUtilSearchArray (
CurrentBuf1Ptr = Buf1;
while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
UINT8 *SourceBufPtr;
- UINT8 *PatternBufPtr;
+ CONST UINT8 *PatternBufPtr;
UINTN PatternBufLength;
SourceBufPtr = CurrentBuf1Ptr;
PatternBufPtr = Buf2;
@@ -375,7 +375,7 @@ PcieUtilGetWrapperLaneBitMap (
VOID
PciePortProgramRegisterTable (
- IN PCIE_PORT_REGISTER_ENTRY *Table,
+ CONST IN PCIE_PORT_REGISTER_ENTRY *Table,
IN UINTN Length,
IN PCIe_ENGINE_CONFIG *Engine,
IN BOOLEAN S3Save,
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
index 7ddaf927533f..1f86ea6ba2d8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
@@ -66,7 +66,7 @@ BOOLEAN
PcieUtilSearchArray (
IN UINT8 *Buf1,
IN UINTN Buf1Length,
- IN UINT8 *Buf2,
+ CONST IN UINT8 *Buf2,
IN UINTN Buf2Length
);
@@ -112,7 +112,7 @@ PcieUtilGetWrapperLaneBitMap (
VOID
PciePortProgramRegisterTable (
- IN PCIE_PORT_REGISTER_ENTRY *Table,
+ CONST IN PCIE_PORT_REGISTER_ENTRY *Table,
IN UINTN Length,
IN PCIe_ENGINE_CONFIG *Engine,
IN BOOLEAN S3Save,
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
index d546f90dfe0a..26d33b1ab1e9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
@@ -342,8 +342,8 @@ PcieTrainingDetectPresence (
}
}
-UINT8 FailPattern1 [] = {0x2a, 0x6};
-UINT8 FailPattern2 [] = {0x2a, 0x9};
+CONST UINT8 FailPattern1 [] = {0x2a, 0x6};
+CONST UINT8 FailPattern2 [] = {0x2a, 0x9};
/*----------------------------------------------------------------------------------------*/
/**
@@ -862,4 +862,4 @@ PcieTrainingDebugDumpPortState (
CurrentEngine->Type.Port.TimeStamp
);
}
-) \ No newline at end of file
+)