diff options
Diffstat (limited to 'src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c | 514 |
1 files changed, 242 insertions, 272 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c index 0b51b4b7fbbc..7341ae3c0dde 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c @@ -67,7 +67,7 @@ DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_SRAMIndex(DRAMC_CTX_T *p, DRAM_DFS_SR return &pFreqTbl[u1ShuffleIdx]; } -#if 0 //@Darren, debug codes +#if 0 void DramcWriteShuffleSRAMRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr, u32 u4Data) { U32 ii, u4tmp, u4Offset=0; @@ -97,14 +97,14 @@ void FullRGDump(DRAMC_CTX_T *p, U8 step, U32 u4ShuOffset) U8 u1RankIdx=0; mcSHOW_DBG_MSG(("[FullRGDump] STEP%d\n", step)); - //Darren-DumpAoNonShuReg(); + for (u1RankIdx=RANK_0; u1RankIdx<p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); mcSHOW_DBG_MSG(("[FullRGDump] RANK%d\n", u1RankIdx)); DumpAoShuReg(u4ShuOffset, u4ShuOffset); } - //Darren-DumpNaoReg(); + } U32 SramDebugModeRead(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg) @@ -124,17 +124,17 @@ U32 SramDebugModeRead(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg) #endif }; - //Backup regs + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); - //vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1 + //vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); // SHU8 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; - u4Value = u4IO32Read4B(DRAMC_REG_ADDR(u4Reg));// SHU1 + u4Value = u4IO32Read4B(DRAMC_REG_ADDR(u4Reg)); DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; mcSHOW_DBG_MSG(("[SramDebugModeRead] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Value)); @@ -161,16 +161,16 @@ void SramDebugModeWrite(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg, U32 u4Data #endif }; - //Backup regs + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); // SHU8 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; - vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1 + vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; mcSHOW_DBG_MSG(("[SramDebugModeWrite] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Data)); @@ -182,7 +182,7 @@ void SramDebugModeWrite(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg, U32 u4Data void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) { U32 ii, u4tmp, u4Offset=0; - DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; // SHU1 need use p->ShuRGAccessIdx=DRAM_DFS_REG_SHU1 for RK1 + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) { @@ -201,7 +201,7 @@ void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) { U32 ii, u4tmp, u4Offset=0; - DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; // SHU1 need use p->ShuRGAccessIdx=DRAM_DFS_REG_SHU1 for RK1 + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) { @@ -230,31 +230,31 @@ void CmdBusTrainingLP4YWA(DRAMC_CTX_T *p, U8 u1OnOff) { U8 u1MR51 = 0; - if ((p->frequency > 800) && (p->dram_fsp==FSP_0)) // skip DDR1600 up + if ((p->frequency > 800) && (p->dram_fsp==FSP_0)) return; - if (p->dram_fsp==FSP_1) //for HIGH speed in FSP1, FSP0 SE setting will be mismatch + if (p->dram_fsp==FSP_1) { if (u1OnOff==DISABLE) { p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; - //CLK to Diff end + ClkSingleEndRGEnable ( p, u1OnOff); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; } } - else //for LOW speed under DDR1600 + else { if (u1OnOff == DISABLE) - u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] & ~(1 << 3); // disable CLK SE mode + u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] & ~(1 << 3); else - u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] | (1 << 3); // enable CLK SE mode + u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] | (1 << 3); DramcModeRegWriteByRank(p, p->rank, 51, u1MR51Value[p->dram_fsp]); - //CLK to Diff end + ClkSingleEndRGEnable ( p, u1OnOff); } } @@ -276,10 +276,10 @@ void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level) mcSHOW_DBG_MSG(("[DFSRuntimeMRW_preset_BeforeK] FSP%d\n", p->dram_fsp)); #endif -#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 1) //Set SE before Calibration +#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 1) if (p->frequency <=800) { - u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; // CLK[3]=1, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y + u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; } else { @@ -287,7 +287,7 @@ void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level) } #endif - //! save shux mr1/mr2/mr3/mr11 + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4), P_Fld(u1MR01Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0) | P_Fld(u1MR02Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1) | @@ -296,7 +296,7 @@ void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level) #if ENABLE_RTMRW_DEBUG_LOG mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR11 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03Value[p->dram_fsp], u1MR11Value[p->dram_fsp])); #endif - //! save shux mr22/mr51 + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4), P_Fld(u1MR21Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5) | P_Fld(u1MR22Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6) | @@ -310,10 +310,10 @@ void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level) #if CHANNEL_NUM > 2 if (channel_num_auxadc > 2) { if (u1ChIdx >= CHANNEL_C) - u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); // for 4ch others DPM + u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); } #endif - //! save shux mr12/mr14 + vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + u4DPMOffset + (sram_shu_level << 4), P_Fld(u1MR12Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8) | P_Fld(u1MR12Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9) | @@ -349,10 +349,10 @@ void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level) u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0x7F) | (p->DBI_W_onoff[p->dram_fsp] << 7)); #endif -#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 0) //Set SE after Calibration +#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 0) if (p->frequency <=800) { - u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; // CLK[3]=1, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y + u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; } else { @@ -360,13 +360,13 @@ void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level) } #endif - //! save shux mr1/mr2/mr3/mr11 + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4), u1MR03_Value, LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2); #if ENABLE_RTMRW_DEBUG_LOG mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR11 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03_Value, u1MR11Value[p->dram_fsp])); #endif - //! save shux mr22/mr51 + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4), u1MR51_Value, LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7); #if ENABLE_RTMRW_DEBUG_LOG @@ -378,10 +378,10 @@ void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level) #if CHANNEL_NUM > 2 if (channel_num_auxadc > 2) { if (u1ChIdx >= CHANNEL_C) - u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); // for 4ch others DPM + u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); } #endif - //! save shux mr12/mr14 + vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + u4DPMOffset + (sram_shu_level << 4), P_Fld(u1MR12Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8) | P_Fld(u1MR12Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9) | @@ -403,15 +403,15 @@ void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level) static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1MR1, U8 u1MR2, U8 u1MR3, U8 u1MR11, U8 u1MR12, U8 u1MR13, U8 u1MR14, U8 u1MR21, U8 u1MR22, U8 u1MR51) { U8 rt_response_ack = 1, rt_ack = 0; - U8 u1MRW_1ST_Num = 0x5; // MR13, MR1, MR2, MR3, MR11, MR12 - U8 u1MRW_2ND_Num = 0x2; // MR14, 22, 51 + U8 u1MRW_1ST_Num = 0x5; + U8 u1MRW_2ND_Num = 0x2; #if ENABLE_LP4Y_DFS - u1MRW_2ND_Num++; // for LP4Y MR21 + u1MRW_2ND_Num++; #endif #if 1 - //! MR13, MR1, MR2, MR3, MR11, MR12 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0), P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) | P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) | @@ -423,28 +423,28 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) | P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT)); - //! MA = 13, 1, 2, 3 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1), P_Fld(13, RTMRW_CTRL1_RTMRW0_MA) | P_Fld(1, RTMRW_CTRL1_RTMRW1_MA) | P_Fld(2, RTMRW_CTRL1_RTMRW2_MA) | P_Fld(3, RTMRW_CTRL1_RTMRW3_MA)); - //! OP13, OP1, OP2, OP3 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2), P_Fld(u1MR13, RTMRW_CTRL2_RTMRW0_OP) | P_Fld(u1MR1, RTMRW_CTRL2_RTMRW1_OP) | P_Fld(u1MR2, RTMRW_CTRL2_RTMRW2_OP) | P_Fld(u1MR3, RTMRW_CTRL2_RTMRW3_OP)); - //! MR11/MR12 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL3), P_Fld(11, RTMRW_CTRL3_RTMRW4_MA) | P_Fld(12, RTMRW_CTRL3_RTMRW5_MA) | P_Fld(u1MR11, RTMRW_CTRL3_RTMRW4_OP) | P_Fld(u1MR12, RTMRW_CTRL3_RTMRW5_OP)); - //!runtime MRW trigger + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN); do { @@ -455,7 +455,7 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M #endif #if 1 - //! MR14/22/51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0), P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) | P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) | @@ -467,7 +467,7 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) | P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT)); - //! MA = 14, 22, 51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1), P_Fld(14, RTMRW_CTRL1_RTMRW0_MA) | #if ENABLE_LP4Y_DFS @@ -476,7 +476,7 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M P_Fld(22, RTMRW_CTRL1_RTMRW1_MA) | P_Fld(51, RTMRW_CTRL1_RTMRW2_MA)); - //! OP14, OP22, OP51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2), P_Fld(u1MR14, RTMRW_CTRL2_RTMRW0_OP) | #if ENABLE_LP4Y_DFS @@ -485,7 +485,7 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M P_Fld(u1MR22, RTMRW_CTRL2_RTMRW1_OP) | P_Fld(u1MR51, RTMRW_CTRL2_RTMRW2_OP)); - //!runtime MRW trigger + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN); do { @@ -505,9 +505,9 @@ static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_s mcSHOW_DBG_MSG(("[DFSRTMRW_HwsetWA] \n")); #endif - p->ShuRGAccessIdx = cur_shu_mux_index; // Currect + p->ShuRGAccessIdx = cur_shu_mux_index; u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP); - p->ShuRGAccessIdx = pingpong_shu_level; // Next + p->ShuRGAccessIdx = pingpong_shu_level; u1VRCG_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), SHU_HWSET_VRCG_HWSET_VRCG_OP); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; @@ -515,26 +515,26 @@ static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_s { if (cur_shu_mux_index == PHYPLL_MODE) { - u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL - u1VRCG_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + u1MR13_OP &= 0x3F; + u1VRCG_OP &= 0x3F; } else { - u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL - u1VRCG_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + u1MR13_OP |= 0xC0; + u1VRCG_OP |= 0xC0; } } else { if (cur_shu_mux_index == PHYPLL_MODE) { - u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL - u1VRCG_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + u1MR13_OP |= 0xC0; + u1VRCG_OP |= 0xC0; } else { - u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL - u1VRCG_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + u1MR13_OP &= 0x3F; + u1VRCG_OP &= 0x3F; } } @@ -548,10 +548,10 @@ static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_s bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - p->ShuRGAccessIdx = cur_shu_mux_index; // Currect - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); // Current - p->ShuRGAccessIdx = pingpong_shu_level; // Next - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), u1VRCG_OP, SHU_HWSET_VRCG_HWSET_VRCG_OP); // Next + p->ShuRGAccessIdx = cur_shu_mux_index; + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); + p->ShuRGAccessIdx = pingpong_shu_level; + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), u1VRCG_OP, SHU_HWSET_VRCG_HWSET_VRCG_OP); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; if (CH_num > CHANNEL_SINGLE) DramcBroadcastOnOff(bc_bak); @@ -573,14 +573,12 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); ch_bak = vGetPHY2ChannelMapping(p); - //! get mr13 - //rtmr13 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0, LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0); - //! get shux mr1/mr2/mr3/mr11 + rtmr1 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0); rtmr2 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1); rtmr3 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2); rtmr11 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3); - //! get shux mr21/mr22/mr51 + rtmr21 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5); rtmr22 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6); rtmr51 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7); @@ -589,16 +587,16 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev if (p->boot_fsp== FSP_1) { if(cur_shu_mux_index == PHYPLL_MODE) - rtmr13 |= (0x1 << 7); //! MR13 OP7 = 1, OP6 = 0, from PHYPLL to CLRPLL + rtmr13 |= (0x1 << 7); else - rtmr13 |= (0x1 << 6); //! MR13 OP7 = 0, OP6 = 1, from CLRPLL to PHYPLL + rtmr13 |= (0x1 << 6); } else { if(cur_shu_mux_index == PHYPLL_MODE) - rtmr13 |= (0x1 << 6); //! MR13 OP7 = 0, OP6 = 1, from CLRPLL to PHYPLL + rtmr13 |= (0x1 << 6); else - rtmr13 |= (0x1 << 7); //! MR13 OP7 = 1, OP6 = 0, from PHYPLL to CLRPLL + rtmr13 |= (0x1 << 7); } #if ENABLE_RTMRW_DEBUG_LOG mcSHOW_DBG_MSG(("[DFSRuntimeMRWEn]\n")); @@ -613,7 +611,7 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev #if (CHANNEL_NUM > 2) if (channel_num_auxadc > 2) { if (u1ChIdx >= CHANNEL_C) - DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM);//SHIFT_TO_CHB_ADDR; + DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); else } #endif @@ -621,7 +619,7 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { - //! get shux mr12/mr14/ + rtmr12 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + DPMOffset + (nxt_shu_level << 4), Fld(8, u1RankIdx*8)); rtmr14 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + DPMOffset + (nxt_shu_level << 4), Fld(8, (u1RankIdx*8)+16)); #if ENABLE_RTMRW_DEBUG_LOG @@ -648,13 +646,13 @@ static void DFSHwSetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level, U #if ENABLE_RTMRW_DEBUG_LOG mcSHOW_DBG_MSG(("[DFSHwSetWA] \n")); #endif - p->ShuRGAccessIdx = cur_shu_mux_index; // NOTE: Currect shuffle + p->ShuRGAccessIdx = cur_shu_mux_index; u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP); - if ((nxt_shu_level == SRAM_SHU0) || (nxt_shu_level == SRAM_SHU1)) // for term shuffle level - u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + if ((nxt_shu_level == SRAM_SHU0) || (nxt_shu_level == SRAM_SHU1)) + u1MR13_OP |= 0xC0; else - u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + u1MR13_OP &= 0x3F; if (CH_num > CHANNEL_SINGLE) { @@ -666,7 +664,7 @@ static void DFSHwSetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level, U mcSHOW_DBG_MSG(("HWSET_MR13_OP = 0x%x\n", u1MR13_OP)); #endif - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); // Current + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); if (CH_num > CHANNEL_SINGLE) DramcBroadcastOnOff(bc_bak); @@ -700,7 +698,7 @@ void ConfigMCK4To1MUX(DRAMC_CTX_T *p, CLK_MUX_T eClkMux) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, P_Fld(0x3, MISC_CG_CTRL0_CLK_MEM_SEL) | P_Fld(0x1, MISC_CG_CTRL0_W_CHG_MEM)); - mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + mcDELAY_XNS(100); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_W_CHG_MEM); } @@ -772,19 +770,19 @@ static void ChkDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode) { WaitDFSDebugSM(p, 0x1e); - // HW shuffle will switch clock to 208MHz and continue DFS + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); - mcDELAY_US(1); // Wait 1T 26MHz + mcDELAY_US(1); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); WaitDFSDebugSM(p, 0x1f); - // HW shuffle will switch clock to MCK and continue DFS + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); - mcDELAY_US(1); // Wait 1T 26MHz + mcDELAY_US(1); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); @@ -814,10 +812,8 @@ static void EntryDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode) { vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN) | P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN)); - // for DPM RG mode + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); - // for PHY RG mode (no support) - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); } else { @@ -836,13 +832,11 @@ U32 u4PERFCTL0_backup=0; void EnableDFSNoQueueFlush(DRAMC_CTX_T *p) { vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0, DVFS_CTRL0_HWSET_WLRL) - | P_Fld(0, DVFS_CTRL0_DVFS_RXFIFOST_SKIP) // sync MP settings + | P_Fld(0, DVFS_CTRL0_DVFS_RXFIFOST_SKIP) | P_Fld(1, DVFS_CTRL0_DVFS_NOQUEFLUSH_EN) | P_Fld(0, DVFS_CTRL0_R_DMDVFSMRW_EN)); vIO32WriteFldMulti_All(DRAMC_REG_SHUCTRL1, P_Fld(0, SHUCTRL1_FC_PRDCNT) #if ENABLE_LP4Y_WA - //@Berson, LP4Y tCKFSPE/X_SE violation at shuffle as DVFS noqueflush enable - // LP4Y tCKFSPE/X_SE violation at shuffle from 7.5ns to 15ns | P_Fld(5, SHUCTRL1_CKFSPE_PRDCNT) | P_Fld(5, SHUCTRL1_VRCGEN_PRDCNT) #else @@ -850,27 +844,27 @@ void EnableDFSNoQueueFlush(DRAMC_CTX_T *p) | P_Fld(0, SHUCTRL1_VRCGEN_PRDCNT) #endif | P_Fld(0, SHUCTRL1_CKFSPX_PRDCNT)); - vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0, BYPASS_FSPOP_BPFSP_OPT); // sync MP settings + vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0, BYPASS_FSPOP_BPFSP_OPT); -#if ENABLE_DFS_RUNTIME_MRW // for Skip HW MR2 - vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP) // OP CHG & VRCG High - | P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP) // VRCG Low - | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP)); // MR2 RL/WL (reduce 50ns) +#if ENABLE_DFS_RUNTIME_MRW + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP) + | P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP) + | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP)); #endif #if ENABLE_DFS_NOQUEUE_FLUSH_DBG - // for debug mode only (skip HW MRW) + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE) | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE) | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE)); #endif - //Fix wdle cnt fail issue + vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 1, MISCTL0_GROUP_A_REV); } #if 0 static void WaitNoQueueFlushComplete(DRAMC_CTX_T *p) { - // for debug mode only + U8 u1tCKFSPe_OK[CHANNEL_NUM] = {0}; U8 u1tVRCGDis_OK[CHANNEL_NUM] = {0}; U8 u1ChIdx = 0; @@ -928,7 +922,7 @@ static void TimingTxsrWA(DRAMC_CTX_T *p, U32 next_shu_level) { U32 onoff=0, bc_bak=0; - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) { bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); @@ -961,23 +955,23 @@ void TxReadBaseODTWA(DRAMC_CTX_T *p, U8 next_shu_level) { U32 termen_dis, bc_bak=0; - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) { bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - if ((next_shu_level == SRAM_SHU0) || (next_shu_level == SRAM_SHU1)) // for DDR4266/DDR3200 - termen_dis = DISABLE; //term + if ((next_shu_level == SRAM_SHU0) || (next_shu_level == SRAM_SHU1)) + termen_dis = DISABLE; else - termen_dis = ENABLE; // un-term + termen_dis = ENABLE; //mcSHOW_DBG_MSG(("[TxReadBaseODTWA] SRAM SHU%d, termen_dis = %d\n", next_shu_level, termen_dis)); vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, termen_dis, B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0); vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, termen_dis, B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1); vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, termen_dis, CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS); - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) DramcBroadcastOnOff(bc_bak); } #endif @@ -987,7 +981,7 @@ static void TxReBaseWDQSDqsPiWA(DRAMC_CTX_T *p, U8 pingpong_shu_level) { U32 bc_bak=0; - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) { bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); @@ -1005,7 +999,7 @@ static void TxReBaseWDQSDqsPiWA(DRAMC_CTX_T *p, U8 pingpong_shu_level) | P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 ) ); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) DramcBroadcastOnOff(bc_bak); } #endif @@ -1018,13 +1012,13 @@ static void DDR800_SOPEN_DSC_WA(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff) if (p->DRAMPinmux != PINMUX_DSC) return; - if (p->support_channel_num> CHANNEL_SINGLE) //for dual single + if (p->support_channel_num> CHANNEL_SINGLE) { bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - if ((next_shu_level == SRAM_SHU6) && (u1OnOff==DISABLE))// for DDR800 + if ((next_shu_level == SRAM_SHU6) && (u1OnOff==DISABLE)) { MPDIV_CG = DISABLE; vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG); @@ -1042,15 +1036,15 @@ static void DDR800_SOPEN_DSC_WA(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff) void EnableDFSHwModeClk(DRAMC_CTX_T *p) { - //Shuffle HW mode for MCK/208M switch + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, - P_Fld(0x3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI) | // dvfs source clock selection when ddrphy shuffle - P_Fld(0x1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE)); // dvfs destination clock selection when ddrphy shuffle + P_Fld(0x3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI) | + P_Fld(0x1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE)); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, - P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN) | //M_CK clock mux selection update enable by shuffle - P_Fld(0x1, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) | // by shuffle - P_Fld(0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE) | // HW mode by shuffle - P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL)); // 4-to-1 mux for PLLCK + P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN) | + P_Fld(0x1, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) | + P_Fld(0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE) | + P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL)); } #if 0 static void DFSEnlargeTimingSettings(DRAMC_CTX_T *p) @@ -1072,33 +1066,30 @@ static void DFSEnlargeTimingSettings(DRAMC_CTX_T *p) #endif void DVFSSettings(DRAMC_CTX_T *p) { - U8 u1DVFS_52M_104M_SEL = 1; // DVFS_SM freq: 0: 52Mhz 1:104Mhz - U8 u1Master_DLL_Idle = 0x2b; // Master from MCK - U8 u1Slave_DLL_Idle = 0x43; // Slave from MCK -#if (fcFOR_CHIP_ID == fcA60868) // @Darren, for A60868 only - U8 u1ChClkIgnore[2] = {ENABLE, ENABLE}, u1Channel = 0; // 1=ignore + U8 u1DVFS_52M_104M_SEL = 1; + U8 u1Master_DLL_Idle = 0x2b; + U8 u1Slave_DLL_Idle = 0x43; +#if (fcFOR_CHIP_ID == fcA60868) + U8 u1ChClkIgnore[2] = {ENABLE, ENABLE}, u1Channel = 0; #endif U32 backup_broadcast = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); if (vGet_Div_Mode(p) == DIV16_MODE) { - u1Master_DLL_Idle = 0x37; // Master from MCK - u1Slave_DLL_Idle = 0x4D; // Slave from MCK + u1Master_DLL_Idle = 0x37; + u1Slave_DLL_Idle = 0x4D; } - //DVFS debug enable - MRR_STATUS2_DVFS_STATE - //@Lynx, A60868 HW always enable shuffle debug. remove RG: DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE - //vIO32WriteFldAlign_All(DRAMC_REG_DVFSDLL, 1, DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL); //Set DVFS_SM's clk + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL); #if ENABLE_DFS_208M_CLOCK - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_RG_104M_208M_SEL); //Set DVFS_SM's clk to 208M + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_RG_104M_208M_SEL); #endif vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(u1Master_DLL_Idle, MISC_SHU_DVFSDLL_R_DLL_IDLE) | P_Fld(u1Slave_DLL_Idle, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); - // @Darren, set current SRAM SHU index for SPM mode DFS latch/restore vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, vGet_Current_SRAMIdx(p), MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM); //mcSHOW_DBG_MSG(("[DVFSSettings] SHU_LEVEL_SRAM = %d\n", vGet_Current_SRAMIdx(p))); @@ -1108,9 +1099,9 @@ void DVFSSettings(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(u1ChClkIgnore[1], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHB) | P_Fld(u1ChClkIgnore[0], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHA)); #endif - // DFS trigger by DDRPHY RG - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); // DFS RG mode for calibration - //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS); // DFS RG mode for disable tx tracking + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_RG_MRW_AFTER_DFS); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1, P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) @@ -1120,10 +1111,10 @@ void DVFSSettings(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_OPT, P_Fld(1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN) | P_Fld(1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN)); #if ENABLE_DFS_HW_SAVE_MASK - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY); // 0x1 = disable dfs hw save + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY); #endif -#if 0 // @Darren, reserved from Mengru Dsim +#if 0 U8 u1MarginNew = (u1DVFS_52M_104M_SEL == 1) ? 0x3 : 0x1; vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_OPT, 0x2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW) @@ -1144,14 +1135,14 @@ void DVFSSettings(DRAMC_CTX_T *p) | P_Fld(1, MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT)); #endif -#if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION // @Mazar +#if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 1, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE) | P_Fld(3, MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN) | P_Fld(3, MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW)); #endif -#if (fcFOR_CHIP_ID == fc8195) // @Darren, for Mar_gaux New setting for ddrphy shuffle (sync mode) +#if (fcFOR_CHIP_ID == fc8195) vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL); vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHB_ADDR, 1, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL); #if CHANNEL_NUM > 2 @@ -1162,8 +1153,7 @@ void DVFSSettings(DRAMC_CTX_T *p) #endif #endif - //DLL_SHUFFLE should be set enable before switch frequency - // @Darren, func is empty after IPM via @Mazar + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_RG_DLL_SHUFFLE); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(0, MISC_DVFSCTL2_R_DVFS_OPTION) @@ -1180,7 +1170,7 @@ void DVFSSettings(DRAMC_CTX_T *p) DFSEnlargeTimingSettings(p); #endif - //EnableDFSHwModeClk(p); // @Darren, for DFS shuffle change + //EnableDFSHwModeClk(p); DramcBroadcastOnOff(backup_broadcast); } @@ -1231,9 +1221,9 @@ static void DramcSSCHoppingOnOff(DRAMC_CTX_T *p, U8 cur_shu_level, U8 u1OnOff) if ((cur_shu_level == 0x0) || (cur_shu_level == 0x8) || (cur_shu_level == 0x9) || (cur_shu_level == 0x6) || (cur_shu_level == 0x5)) { if (!(p->u1PLLMode == PHYPLL_MODE)) - vIO32WriteFldAlign(DDRPHY_REG_CLRPLL0, u1OnOff, CLRPLL0_RG_RCLRPLL_SDM_SSC_EN); // CLRPLL SSC + vIO32WriteFldAlign(DDRPHY_REG_CLRPLL0, u1OnOff, CLRPLL0_RG_RCLRPLL_SDM_SSC_EN); else - vIO32WriteFldAlign(DDRPHY_REG_PHYPLL0, u1OnOff, PHYPLL0_RG_RPHYPLL_SDM_SSC_EN); // PHYPLL SSC + vIO32WriteFldAlign(DDRPHY_REG_PHYPLL0, u1OnOff, PHYPLL0_RG_RPHYPLL_SDM_SSC_EN); } } #endif @@ -1242,28 +1232,23 @@ static void DramcSSCHoppingOnOff(DRAMC_CTX_T *p, U8 cur_shu_level, U8 u1OnOff) #if DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM || ENABLE_DFS_SSC_WA void DVS_DMY_RD_ENTR(DRAMC_CTX_T *p) { - /*TINFO="DRAM : SPM DVS DMY RD ENTR"*/ - /*TINFO="DRAM : set sc_ddrphy_fb_ck_en = 1"*/ vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 1, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_en_mod_sel = 1"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_intv_sel = 1"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_en = 1"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_EN); mcDELAY_US(1); @@ -1271,33 +1256,28 @@ void DVS_DMY_RD_ENTR(DRAMC_CTX_T *p) void DVS_DMY_RD_EXIT(DRAMC_CTX_T *p) { - /*TINFO="DRAM : SPM DVS DMY RD EXIT"*/ - /*TINFO="DRAM : set sc_dmyrd_en = 0"*/ - //! diff with WE vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_EN); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_intv_sel = 0"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_en_mod_sel = 0"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL); mcDELAY_US(1); - /*TINFO="DRAM : set sc_ddrphy_fb_ck_en = 0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); mcDELAY_US(1); - /*TINFO="DRAM : SPM DVS DMY RD EXIT end "*/ + } #endif @@ -1309,11 +1289,11 @@ static void EnableDramcTrackingByShuffle(DRAMC_CTX_T *p, U8 u1EnDPMCh, U8 u1OnOf { #if ENABLE_RX_TRACKING vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnDPMCh, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN); - //RX delay cell use Vmddr in all freq, so rx tracking is not needed. + #endif #if ENABLE_TX_TRACKING vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS); - //The LPDDR4 DRAM cannot be placed in power-down state during "Start DQS Interval Oscillator" operation. + #endif } else if (u1OnOff == DISABLE) @@ -1338,19 +1318,19 @@ static void EnableDramcTrackingBySPMControl(DRAMC_CTX_T *p) static void TransferToRegControl(void) { - /* Chen-Hsiang@20160323: After leave preloader and low power scenario, conf is controller by RG*/ + } -static void TransferToSPMControl(DRAMC_CTX_T *p)//Open all APHY controls from SPM path except PWR_ON && ISO (related to low power and DVFS) +static void TransferToSPMControl(DRAMC_CTX_T *p) { -#if ENABLE_TX_TRACKING //HW mode - vIO32WriteFldAlign_All(DRAMC_REG_TX_TRACKING_SET0, 0x0, TX_TRACKING_SET0_TX_TRACKING_OPT);//Set TX_TRACKING_OPT = 0 to let spm side band control HW TX tracking +#if ENABLE_TX_TRACKING + vIO32WriteFldAlign_All(DRAMC_REG_TX_TRACKING_SET0, 0x0, TX_TRACKING_SET0_TX_TRACKING_OPT); #endif -#if 0 // Low power features remove to others RG: B0_LP_CTRL0/B1_LP_CTRL/CA_LP_CTRL/MISC_LP_CTRL +#if 0 vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0xfbffefff, MISC_SPM_CTRL0_PHY_SPM_CTL0); vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2, 0xffffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2); - vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2 + SHIFT_TO_CHB_ADDR, 0x7fffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2);//Lewis@20170627: Set CHB CA DLL type to slave mode + vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2 + SHIFT_TO_CHB_ADDR, 0x7fffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2); #endif return; @@ -1376,18 +1356,18 @@ void DPMInit(DRAMC_CTX_T *p) u1SetVal = (p->support_channel_num > 1) ? 0x3 : 0x1; - // pre-setting DPM to dramc low power interface setting + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_PHYPLL_EN) | // both channel phy pll en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_EN) | // both channel dpy pll en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN) | // both channel dpy 2nd pll en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN) | // both channel dpy dll ck en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_VREF_EN)); // both channel dpy vref en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_PHYPLL_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_VREF_EN)); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN) | // both channel mck8x en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN) | // both channel midpi en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN)); // both channel dpy pi resetb en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN)); if (p->u1PLLMode == PHYPLL_MODE) { @@ -1408,17 +1388,17 @@ void DPMInit(DRAMC_CTX_T *p) P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN) | P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW)); - // all by lpif fw mode + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1, - /* TBA set control mux in DV initial */ - P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) | // 0: DPM, 1: SPM - P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) | // 0: DPM, 1: SPM - P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) | // 0: DPM, 1: SPM - P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND) | // 0: DPM, 1: SPM - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) | // 0: DPM SCU, 1: DPM CFG - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND) | // 0: DPM SCU, 1: DPM CFG - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL) | // 0: DPM SCU, 1: DPM CFG - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND)); // 0: DPM SCU, 1: DPM CFG + + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) | + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) | + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) | + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND)); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0, P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN) | @@ -1426,7 +1406,7 @@ void DPMInit(DRAMC_CTX_T *p) P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN) | P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN) | P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN) | - P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN) | // @Darren, fix dfs phypll init + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN) | P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW)); u1ShuSramVal = u1CurrShuLevel; @@ -1434,18 +1414,18 @@ void DPMInit(DRAMC_CTX_T *p) if (p->support_channel_num > 1) u1ShuSramVal |= u1CurrShuLevel << 4; - // NOTE: DPM PST mode shuffle level = (LPIF_CTRL_CTRL1_LPIF_DRAMC_DR_SHU_LEVEL_SRAM | LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL) + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ShuSramVal, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL); #if __ETT__ vIO32WriteFldAlign_All(DDRPHY_MD32_REG_SSPM_CFGREG_GPR0, 0xE7700E77, SSPM_CFGREG_GPR0_GPR0); #endif - // for DFS + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN); vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN); - // enable DFD + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 , 0x1, LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN); } #endif @@ -1499,11 +1479,11 @@ void DFSBypassMR13HwSet(DRAMC_CTX_T *p) mcSHOW_ERR_MSG(("[DFSBypassMR13HwSet] fail at BPFSP_SHU%d incorrect !!!\n", u1SramShuIdx)); break; } - BFSP = (gFreqTbl[u1ShuffleIdx].freq_sel <= LP4_DDR2667)? 0x1: 0x0; //0x1 (Bypass), 0x0 (Not bypass) + BFSP = (gFreqTbl[u1ShuffleIdx].freq_sel <= LP4_DDR2667)? 0x1: 0x0; //mcSHOW_DBG_MSG(("[DFSBypassMR13HwSet] BPFSP_SHU%d = 0x%x\n", u1SramShuIdx, BFSP)); vIO32WriteFldAlign_All(TransferReg.u4Addr, BFSP, TransferReg.u4Fld); } - vIO32WriteFldAlign_All(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0, 0x1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); // 1: shuffle level = 10, 0: shuffle level =4 + vIO32WriteFldAlign_All(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0, 0x1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CDC_CTRL, 0x0, MISC_CDC_CTRL_REG_CDC_BYPASS_DBG); vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0x1, BYPASS_FSPOP_BPFSP_OPT); #endif @@ -1557,7 +1537,7 @@ void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T srcRG, DRAM_DFS_S } vSetPHY2ChannelMapping(p, eOriChannel); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0, MISC_SRAM_DMA0_SRAM_WR_MODE); //MP setting:should disable WR MDOE + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0, MISC_SRAM_DMA0_SRAM_WR_MODE); } void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T srcRG, DRAM_DFS_REG_SHU_T dstRG) @@ -1574,8 +1554,8 @@ void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T srcRG, DRAM_DFS_ vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_MODE); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_STEP_EN_MODE); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SRAM_WR_MODE); //diff with DramcSaveToShuffleSRAM - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_APB_WR_MODE); // diff with DramcSaveToShuffleSRAM + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SRAM_WR_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_APB_WR_MODE); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), dstRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_APB); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), srcRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM); @@ -1613,7 +1593,7 @@ static U8 WaitChShuEnAck(DRAMC_CTX_T *p, U32 u4Addr, U32 u4Fld, U8 u1Status) } vSetPHY2ChannelMapping(p, eOriChannel); - return u1AckDone; // shu end + return u1AckDone; } void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level) @@ -1638,7 +1618,7 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le u1ShuAck |= (0x1 << i); } - /* cc: Fix RG mode Hang. Since ACK is read from DPM and a DPM can only support up to 2 dram channels */ + u1SramAck = u1ShuAck; u1ShuAck &= 0x3; @@ -1651,10 +1631,10 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le mcSHOW_DBG_MSG4(("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); } - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); - // sram latch + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH); mcDELAY_US(1); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH); @@ -1675,14 +1655,14 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le } mcDELAY_US(1); -#if 1 //Darren- +#if 1 //vIO32WriteFldMulti((DDRPHY_MISC_SPM_CTRL3), P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH1) // | P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH0)); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM); - //wait sram load ack. + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD); - //while (!u4IO32ReadFldAlign(DDRPHY_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK)); // wait SRAM PLL load ack + //while (!u4IO32ReadFldAlign(DDRPHY_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK)); while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, u1ChkComplete) != u1SramAck) //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK)) { @@ -1694,15 +1674,15 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le if (p->u1PLLMode == PHYPLL_MODE) { //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); - vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); } else { //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); - vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); } - #if 0//ENABLE_DFS_DEBUG_MODE + #if 0 EntryDFSDebugMode(p, CHG_CLK_MODE); #endif @@ -1711,9 +1691,9 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le #endif #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) - mcDELAY_US(20); // for SRAM shuffle DV sim spec > 20us + mcDELAY_US(20); #else - mcDELAY_XUS(20); // for SRAM shuffle DV sim spec > 20us + mcDELAY_XUS(20); #endif #if 0 @@ -1728,22 +1708,21 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le //vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN); mcSHOW_DBG_MSG4(("SHUFFLE Start\n")); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from SHU_EN=1 to ACK, DV spec < 5.1us + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); #if DFS_NOQUEUE_FLUSH_ENABLE && ENABLE_DFS_NOQUEUE_FLUSH_DBG - WaitNoQueueFlushComplete(p); // for debug mode MRW skip + WaitNoQueueFlushComplete(p); #endif - // Fixed DV sim spec for DFS shu_en=1 < 5.1us and shu_en=0 < 120ns -#if 1//Darren-for test chip(FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + +#if 1 //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n")); //mcDELAY_US(5); - #if 0//ENABLE_DFS_DEBUG_MODE + #if 0 ChkDFSDebugMode(p, CHG_CLK_MODE); #endif - //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END - //@tg Fix RG mode can not recevie shuffle end ack. + if (channel_num_auxadc <= 2) { while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck) { @@ -1759,10 +1738,10 @@ else { } #else - while (u4IO32ReadFldAlign(DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE) != u1ShuAckState); // SHUFFLE_END + while (u4IO32ReadFldAlign(DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE) != u1ShuAckState); #endif - #if 0//ENABLE_DFS_DEBUG_MODE + #if 0 ExitDFSDebugMode(p, CHG_CLK_MODE); #endif @@ -1775,7 +1754,7 @@ else { #endif //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from ACK to SHU_EN=0, DV spec < 120ns + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); mcSHOW_DBG_MSG4(("SHUFFLE End\n")); #if ENABLE_DDR800_SOPEN_DSC_WA @@ -1790,19 +1769,16 @@ else { if (p->u1PLLMode == PHYPLL_MODE) { - /*TINFO="DRAM : set sc_phypll_mode_sw=0"*/ - //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); // Disable PHYPLL - vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); } else { - /*TINFO="DRAM : set sc_phypll2_mode_sw=0"*/ - //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); // Disable CLRPLL - vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); } -#if 1 //Darren- - //wait sram restore ack. +#if 1 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE); while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, u1ChkComplete) != u1SramAck) //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK)) @@ -1811,7 +1787,7 @@ else { } vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE); - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); #endif @@ -1849,7 +1825,7 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level) u1ShuAck |= (0x1 << i); } - /* cc: Fix RGmode Hang. Since ACK is read from DPM and a DPM can only support up to 2 dram channels */ + u1ShuAck &= 0x3; if (p->u1PLLMode == PHYPLL_MODE) @@ -1861,13 +1837,13 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level) mcSHOW_DBG_MSG4(("DFSDirectJump_RGMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); } - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); if (shu_level == DRAM_DFS_REG_SHU0) - u1shu_level = shu_level; // Darren: shuffle to shu0 status (original calib flow.) + u1shu_level = shu_level; else - u1shu_level = 1; // Darren: Using shu1 for backup/restore, it diff with SPM mode + u1shu_level = 1; if (p->u1PLLMode == PHYPLL_MODE) { @@ -1888,18 +1864,18 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level) if (p->u1PLLMode == PHYPLL_MODE) { //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); - vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); } else { //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); - vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); } #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) - mcDELAY_US(20); // for SRAM shuffle DV sim spec > 20us + mcDELAY_US(20); #else - mcDELAY_XUS(20); // for SRAM shuffle DV sim spec > 20us + mcDELAY_XUS(20); #endif #if 0 @@ -1919,8 +1895,8 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level) //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n")); //mcDELAY_US(5); - //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END - //@tg Fix RG mode can not recevie shuffle end ack. + //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) + if (channel_num_auxadc <= 2) { while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck) { @@ -1949,18 +1925,18 @@ else { if (p->u1PLLMode == PHYPLL_MODE) { - /*TINFO="DRAM : set sc_phypll_mode_sw=0"*/ - //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); // Disable PHYPLL - vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); } else { - /*TINFO="DRAM : set sc_phypll2_mode_sw=0"*/ - //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); // Disable CLRPLL - vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); } - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); mcSHOW_DBG_MSG4(("Shuffle flow complete\n")); @@ -1974,7 +1950,7 @@ void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level) U8 u1ShuAck = 0, u1EnDPMCh = 0; U8 u1ChIdx = 0; U8 u1ChNum_dpm = (p->support_channel_num==CHANNEL_SINGLE)?0x1:0x2; - U8 pingpong_shu_level = 0; // for shu0/1 + U8 pingpong_shu_level = 0; U8 u1PingPong = 0; U16 u2SramLevel = 0; @@ -1993,16 +1969,15 @@ void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level) mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); } - //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x1, MISC_STBCAL2_STB_DBG_STATUS); // HJ Huang - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x1, MISC_STBCAL2_STB_DBG_STATUS); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnDPMCh, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH); mcDELAY_US(1); vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH); - //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[1:0] for CHA - //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[3:2] for CHB - pingpong_shu_level = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10, LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL); // read shuffle level for dramc conf0/1 + + pingpong_shu_level = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10, LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL); mcSHOW_DBG_MSG4(("Ping-pong CONF%d\n", (pingpong_shu_level & 0x1))); for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++) { @@ -2031,7 +2006,7 @@ void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level) DFSRuntimeMRWEn(p, p->u1PLLMode, shu_level); #endif -#if 0 //Darren test+ +#if 0 vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, 0, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL); vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, shu_level, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL); #else @@ -2089,10 +2064,10 @@ else { mcDELAY_US(20); - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); //func_imp_tracking_value_backup(); @@ -2101,8 +2076,8 @@ else { #if ENABLE_DFS_SSC_WA DVS_DMY_RD_EXIT(p); - //DramcSSCHoppingOnOff(p, cur_shu_level, ENABLE); // for waveform measure - //mcDELAY_US(10); // for waveform measure + //DramcSSCHoppingOnOff(p, cur_shu_level, ENABLE); + //mcDELAY_US(10); #endif #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION @@ -2119,7 +2094,7 @@ else { #if ENABLE_DFS_DEBUG_MODE ChkDFSDebugMode(p, CHG_CLK_MODE); - // Add WA at here + ExitDFSDebugMode(p, CHG_CLK_MODE); #endif @@ -2139,8 +2114,8 @@ else { } } #if DFS_NOQUEUE_FLUSH_LATENCY_CNT - U8 MaxCnt = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_RESERVED_6, LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK); // show chx max cnt - // cnt * 8 * 4.8ns (208M) + U8 MaxCnt = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_RESERVED_6, LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK); + mcSHOW_DBG_MSG2(("\tMAX CNT = %d\n", MaxCnt)); #endif @@ -2156,9 +2131,9 @@ else { mcSHOW_DBG_MSG4(("SHUFFLE End\n")); if (p->u1PLLMode == PHYPLL_MODE) - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // PHYPLL off + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); else - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // CLRPLL off + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION DDR800semiPowerSavingOn(p, shu_level, ENABLE); @@ -2177,7 +2152,7 @@ else { #endif //func_imp_tracking_on(); -#if 1 //Darren test+ +#if 1 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnDPMCh, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE); if (channel_num_auxadc <= 2) { @@ -2198,13 +2173,10 @@ else { vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE); #endif - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); EnableDramcTrackingByShuffle(p, u1EnDPMCh, ENABLE); - //----------------------------------- - // TRIGGER DRAM GATING ERROR - //----------------------------------- //func_dram_dummy_read_on(); //mcDELAY_US(2); //func_dram_dummy_read_off(); @@ -2239,8 +2211,7 @@ void DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_leve mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode_forK to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); } - //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[1:0] for CHA - //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[3:2] for CHB + mcSHOW_DBG_MSG4(("Direct jump to CONF%d\n", shu_level)); for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++) { @@ -2270,10 +2241,10 @@ void DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_leve mcDELAY_US(20); - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); @@ -2299,11 +2270,11 @@ else { mcSHOW_DBG_MSG4(("SHUFFLE End\n")); if (p->u1PLLMode == PHYPLL_MODE) - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // PHYPLL off + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); else - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // CLRPLL off + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); + - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); p->u1PLLMode = !p->u1PLLMode; @@ -2316,19 +2287,19 @@ else { void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level) { #if (DRAMC_DFS_MODE == 2) - gDVFSCtrlSel = 2; // SRAM RG mode + gDVFSCtrlSel = 2; #elif (DRAMC_DFS_MODE == 1) - gDVFSCtrlSel = 1; // DPM mode + gDVFSCtrlSel = 1; #elif (DRAMC_DFS_MODE == 0) - gDVFSCtrlSel = 0; // Legacy mode + gDVFSCtrlSel = 0; #endif if (gDVFSCtrlSel == 0) { - if (shu_level == SRAM_SHU0) // DDR4266 - DramcDFSDirectJump_RGMode(p, 0); // Legacy mode for CONF0 + if (shu_level == SRAM_SHU0) + DramcDFSDirectJump_RGMode(p, 0); else - DramcDFSDirectJump_RGMode(p, 1); // Legacy mode for CONF1 + DramcDFSDirectJump_RGMode(p, 1); } else if (gDVFSCtrlSel == 1) { @@ -2342,9 +2313,9 @@ void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level) #if 0 static void No_Parking_On_CLRPLL(DRAMC_CTX_T *p) { - if (p->u1PLLMode == PHYPLL_MODE) return; /* already parking on PHYPLL */ + if (p->u1PLLMode == PHYPLL_MODE) return; - DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU0); /* parking on PHYPLL */ + DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU0); } #endif void ShuffleDfsToOriginalFSP(DRAMC_CTX_T *p) @@ -2352,8 +2323,7 @@ void ShuffleDfsToOriginalFSP(DRAMC_CTX_T *p) U8 operating_fsp = p->dram_fsp; U8 u1RankIdx, backup_rank= u1GetRank(p); - // Support single rank and dual ranks - // Double confirm from CLRPLL to PHYPLL + if (operating_fsp == FSP_1) { cbt_dfs_mr13_global(p, CBT_HIGH_FREQ); |