diff options
Diffstat (limited to 'src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c | 697 |
1 files changed, 334 insertions, 363 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index 02ba35766436..e7e8f899a565 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -28,29 +28,29 @@ bool gUpdateHighestFreq = FALSE; SAVE_TIME_FOR_CALIBRATION_T SavetimeData; #endif -U8 gHQA_Test_Freq_Vcore_Level = 0; // 0: only 1 freq , others are multi freq 1: low vcore 2: high vcore +U8 gHQA_Test_Freq_Vcore_Level = 0; -u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733 +u8 ett_fix_freq = 0xff; DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { - {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. - {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, + {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION {LP4_DDR400 /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF, OPEN_LOOP_MODE}, #endif - {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) - {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, + {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, + {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, }; DRAMC_CTX_T DramCtx_LPDDR4 = { - CHANNEL_SINGLE, // Channel number - CHANNEL_A, // DRAM_CHANNEL - RANK_DUAL, //DRAM_RANK_NUMBER_T - RANK_0, //DRAM_RANK_T + CHANNEL_SINGLE, + CHANNEL_A, + RANK_DUAL, + RANK_0, #ifdef MTK_FIXDDR1600_SUPPORT LP4_DDR1600, @@ -66,71 +66,71 @@ DRAMC_CTX_T DramCtx_LPDDR4 = #endif #endif #if DV_SIMULATION_LP4 - TYPE_LPDDR4X, // DRAM_DRAM_TYPE_T + TYPE_LPDDR4X, #else TYPE_LPDDR5, #endif - FSP_0 , //// DRAM Fast switch point type, only for LP4, useless in LP3 - FSP_0 , //// boot_fsp + FSP_0 , + FSP_0 , ODT_OFF, - {CBT_NORMAL_MODE, CBT_NORMAL_MODE}, // bring up LP4X rank0 & rank1 use normal mode + {CBT_NORMAL_MODE, CBT_NORMAL_MODE}, #if ENABLE_READ_DBI - {DBI_OFF,DBI_ON}, //read DBI + {DBI_OFF,DBI_ON}, #else - {DBI_OFF,DBI_OFF}, //read DBI + {DBI_OFF,DBI_OFF}, #endif #if ENABLE_WRITE_DBI - {DBI_OFF,DBI_ON}, // write DBI + {DBI_OFF,DBI_ON}, #else - {DBI_OFF,DBI_OFF}, // write DBI + {DBI_OFF,DBI_OFF}, #endif - DATA_WIDTH_16BIT, // DRAM_DATA_WIDTH_T - DEFAULT_TEST2_1_CAL, // test2_1; - DEFAULT_TEST2_2_CAL, // test2_2; + DATA_WIDTH_16BIT, + DEFAULT_TEST2_1_CAL, + DEFAULT_TEST2_2_CAL, #if ENABLE_K_WITH_WORST_SI_UI_SHIFT - TEST_WORST_SI_PATTERN, // test_pattern; + TEST_WORST_SI_PATTERN, #else TEST_XTALK_PATTERN, #endif #if (DV_SIMULATION_LP4 == 1) - 800, // frequency - 800, // freqGroup + 800, + 800, #else 1600, 1600, #endif - 0x88, //vendor_id initial value + 0x88, REVISION_ID_MAGIC, - 0xff, //density + 0xff, {0,0}, - 270, // u2DelayCellTimex100; + 270, #if PRINT_CALIBRATION_SUMMARY - //aru4CalResultFlag[CHANNEL_NUM][RANK_MAX] + {{0,0,}}, - //aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX] + {{0,0,}}, 1, 0, #endif - {0}, //BOOL arfgWriteLevelingInitShif; + {0}, #if SUPPORT_SAVE_TIME_FOR_CALIBRATION - FALSE, //femmc_Ready + FALSE, 0, 0, 0, &SavetimeData, #endif - &gFreqTbl[DRAM_DFS_SRAM_MAX-1], // default is DDR1600 1:8 mode + &gFreqTbl[DRAM_DFS_SRAM_MAX-1], DRAM_DFS_REG_SHU0, TRAINING_MODE2, CBT_PHASE_RISING, - 0, //new CBT pattern + 0, PHYPLL_MODE, DBI_OFF, FSP_MAX, PINMUX_EMCP, - {DISABLE,DISABLE}, // disable 10GB + {DISABLE,DISABLE}, 0, }; @@ -156,31 +156,31 @@ void vSetVcoreByFreq(DRAMC_CTX_T *p) hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr); #elif defined(VCORE_BIN) switch (vGet_Current_SRAMIdx(p)) { - case SRAM_SHU0: //4266 + case SRAM_SHU0: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU0); if (!vcore) #endif vcore = get_vcore_uv_table(0); break; - case SRAM_SHU1: //3200 + case SRAM_SHU1: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU1); if (!vcore) #endif vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(1)) >> 1; break; - case SRAM_SHU2: //2400 - case SRAM_SHU3: //1866 + case SRAM_SHU2: + case SRAM_SHU3: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU2); if (!vcore) #endif vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(2)) >> 1; break; - case SRAM_SHU4: //1600 - case SRAM_SHU5: //1200 - case SRAM_SHU6: //800 + case SRAM_SHU4: + case SRAM_SHU5: + case SRAM_SHU6: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU4); if (!vcore) @@ -190,33 +190,33 @@ void vSetVcoreByFreq(DRAMC_CTX_T *p) } #else switch (vGet_Current_SRAMIdx(p)) { - case SRAM_SHU0: // 4266 + case SRAM_SHU0: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU0); #else vcore = SEL_PREFIX_VCORE(LP4, KSHU0); #endif break; - case SRAM_SHU1: // 3200 + case SRAM_SHU1: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU1); #else vcore = SEL_PREFIX_VCORE(LP4, KSHU1); #endif break; - case SRAM_SHU2: // 2400 - case SRAM_SHU3: //1866 + case SRAM_SHU2: + case SRAM_SHU3: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU2); #else vcore = SEL_PREFIX_VCORE(LP4, KSHU2); #endif break; - case SRAM_SHU4: //1600 - case SRAM_SHU5: //1200 - case SRAM_SHU6: //800 + case SRAM_SHU4: + case SRAM_SHU5: + case SRAM_SHU6: #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION - case SRAM_SHU7: //400 + case SRAM_SHU7: #endif #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU4); @@ -249,17 +249,17 @@ void vSetVcoreByFreq(DRAMC_CTX_T *p) #ifdef FOR_HQA_REPORT_USED switch (vGet_Current_SRAMIdx(p)) { - case SRAM_SHU0: //3733 - case SRAM_SHU1: //3200 - case SRAM_SHU2: //2400 - case SRAM_SHU3: //1866 - case SRAM_SHU4: //1600 - case SRAM_SHU5: //1200 - case SRAM_SHU6: //800 + case SRAM_SHU0: + case SRAM_SHU1: + case SRAM_SHU2: + case SRAM_SHU3: + case SRAM_SHU4: + case SRAM_SHU5: + case SRAM_SHU6: #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION - case SRAM_SHU7: //400 + case SRAM_SHU7: #endif - gHQA_Test_Freq_Vcore_Level = 0; //only 1 freq + gHQA_Test_Freq_Vcore_Level = 0; break; default: print("[HQA] undefined shuffle level for Vcore (SHU%d)\r\n", vGet_Current_SRAMIdx(p)); @@ -365,7 +365,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) FinalWinPerBit[u1BitIdx].last_pass=p->pSavetimeData->u1RxWinPerbitDQ_lastbypass_Save[p->channel][p->rank][u1BitIdx+RUNTIME_SHMOO_TEST_BYTE*8]; } - //find smallest first and largest last pass + for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) { if (FinalWinPerBit[u1BitIdx].first_pass < rx_first_delay) @@ -390,10 +390,10 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) #endif if (p->femmc_Ready==0 || - ((p->pSavetimeData->Runtime_Shmoo_para.TX_Channel!=RUNTIME_SHMOO_TEST_CHANNEL) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Rank!=RUNTIME_SHMOO_TEST_RANK) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Byte!=RUNTIME_SHMOO_TEST_BYTE))) //first K + ((p->pSavetimeData->Runtime_Shmoo_para.TX_Channel!=RUNTIME_SHMOO_TEST_CHANNEL) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Rank!=RUNTIME_SHMOO_TEST_RANK) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Byte!=RUNTIME_SHMOO_TEST_BYTE))) { #if RUNTIME_SHMOO_TX - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; //on going + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = tx_pi_delay-32+RUNTIME_SHMOO_TEST_PI_DELAY_START; p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay; @@ -415,7 +415,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) #endif #if RUNTIME_SHMOO_RX - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; //on going + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 0; p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = 0; @@ -429,10 +429,10 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) p->pSavetimeData->Runtime_Shmoo_para.TX_Byte = RUNTIME_SHMOO_TEST_BYTE; #endif } -//fra else if (dramc_get_rshmoo_step()) + else if ((dramc_get_rshmoo_step()) && (p->pSavetimeData->Runtime_Shmoo_para.flag != RUNTIME_SHMOO_END)) { - //judge scan direction + if (RUNTIME_SHMOO_FAST_K == 0) { p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; @@ -467,7 +467,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } else { @@ -503,7 +503,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } } #endif @@ -519,7 +519,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } else { @@ -555,7 +555,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } } #endif @@ -572,7 +572,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } else { @@ -598,7 +598,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } #endif } @@ -627,7 +627,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) print("Fra RunTime Shmoo CH%d, Rank%d, Byte%d\n",RUNTIME_SHMOO_TEST_CHANNEL, RUNTIME_SHMOO_TEST_RANK, RUNTIME_SHMOO_TEST_BYTE ); #endif -//fra if (p->pSavetimeData->Runtime_Shmoo_para.flag != RUNTIME_SHMOO_END) + { #if RUNTIME_SHMOO_TX #if __ETT__ @@ -676,7 +676,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) } DramcTXSetVref(p, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value); - //DLL all off from Justin + #if 0 #if ENABLE_MCK8X_MODE vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_SHU_CA_DLL0), 0x0, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU); @@ -697,41 +697,41 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) #if RUNTIME_SHMOO_RX - // here has a problem, RX dq is perbit but I just can choose one (bit0) to do compare and setting + if (p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0] <=0) { #if 0 - // Set DQS delay + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ P_Fld((-p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]),SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) |P_Fld((-p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]),SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0)); - // Set DQM delay to 0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0) |P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0)); DramPhyReset(p); #endif - // Set DQ delay to 0 + for (u1BitIdx=0; u1BitIdx<4; u1BitIdx++) { - vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE + u1BitIdx*4), 0);//DQ0~DQ7 + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE + u1BitIdx*4), 0); } } else { #if 0 - // Set DQS delay to 0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) |P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0)); - // Adjust DQM output delay. + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ P_Fld(p->pSavetimeData->Runtime_Shmoo_para.RX_delay,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0) |P_Fld(p->pSavetimeData->Runtime_Shmoo_para.RX_delay,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0)); DramPhyReset(p); #endif - // Adjust DQ output delay. + for (u1BitIdx=0; u1BitIdx<8; u1BitIdx+=2) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0+ (DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE) +u1BitIdx*2), \ @@ -741,19 +741,18 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) } } - //Set Vref - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE), p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0); // LP4 and LP4x with term: 0xe + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE), p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0); #endif } - //save parameters to eMMC + #if EMMC_READY write_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData); #endif mcSHOW_ERR_MSG(("Fra Save calibration result to emmc\n")); - //copy parameters to memory for kernel test script used - //wait for YiRong's SRAM copy function + #if RUNTIME_SHMOO_TX dramc_set_rshmoo_info(p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, p->pSavetimeData->Runtime_Shmoo_para.TX_Channel, p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, @@ -765,7 +764,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0], 1, (p->pSavetimeData->Runtime_Shmoo_para.flag == RUNTIME_SHMOO_END) ? 1 : 0); -// vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable +// vAutoRefreshSwitch(p, DISABLE); #endif @@ -775,7 +774,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) #endif -///TODO: wait for porting +++ + #ifdef FIRST_BRING_UP void Test_Broadcast_Feature(DRAMC_CTX_T *p) { @@ -872,7 +871,7 @@ static void vDramCPUReadWriteTestAfterCalibration(DRAMC_CTX_T *p) pass_count=0; #if !__ETT__ - // scy: not to test rank1 (wrong addr 0x0000_0000) + if (u1RankIdx >= 1) continue; #endif @@ -940,7 +939,7 @@ static void vDramCPUReadWriteTestAfterCalibration(DRAMC_CTX_T *p) if(u1DumpInfo) { - // Read gating error flag + #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) DramcDumpDebugInfo(p); #endif @@ -990,13 +989,9 @@ static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p) if (doe_get_config("fullk")) return DRAM_FAIL; - // Parepare fask k data + #if EMMC_READY - // scy: only need to read emmc one time for each boot-up - //if (g_dram_save_time_init_done == 1) - // return DRAM_OK; - //else - // g_dram_save_time_init_done = 1; + if (read_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData) < 0) { p->femmc_Ready = 0; @@ -1007,7 +1002,7 @@ static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p) p->femmc_Ready = 1; } - #else //EMMC is not avaliable, load off-line data + #else if (g_dram_save_time_init_done[vGet_Current_SRAMIdx(p)] == 0) { @@ -1024,7 +1019,7 @@ static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p) if (p->femmc_Ready == 1) { if (p->frequency < 1600) - { // freq < 1600, TX and RX tracking are disable. Therefore, bypass calibration. + { p->Bypass_RDDQC = 1; p->Bypass_RXWINDOW = 1; p->Bypass_TXWINDOW = 1; @@ -1059,24 +1054,24 @@ static void DramRankNumberDetection(DRAMC_CTX_T *p) { U8 u1RankBak; - u1RankBak = u1GetRank(p); // backup current rank setting + u1RankBak = u1GetRank(p); - vSetPHY2ChannelMapping(p, CHANNEL_A); // when switching channel, must update PHY to Channel Mapping + vSetPHY2ChannelMapping(p, CHANNEL_A); vSetRank(p, RANK_1); if (DramcWriteLeveling(p, AUTOK_ON, PI_BASED) == DRAM_OK) { p->support_rank_num = RANK_DUAL; - vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 0, SA_RESERVE_SINGLE_RANK); //keep support_rank_num to reserved rg + vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 0, SA_RESERVE_SINGLE_RANK); } else { p->support_rank_num = RANK_SINGLE; - vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SINGLE_RANK); //keep support_rank_num to reserved rg + vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SINGLE_RANK); } mcSHOW_DBG_MSG2(("[RankNumberDetection] %d\n", p->support_rank_num)); - vSetRank(p, u1RankBak); // restore rank setting + vSetRank(p, u1RankBak); } #endif @@ -1107,17 +1102,17 @@ void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p) { vSetRank(p, s1RankIdx); - vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable + vAutoRefreshSwitch(p, ENABLE); dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0); DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF, NORMAL_K); #if MRW_CHECK_ONLY mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); #endif - vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable + vAutoRefreshSwitch(p, DISABLE); } - vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate()) + vSetRank(p, RANK_0); #if GATING_ADJUST_TXDLY_FOR_TRACKING DramcRxdqsGatingPostProcess(p); @@ -1139,15 +1134,15 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf vSetPHY2ChannelMapping(p, CHANNEL_A); - // Read MR5 for Vendor ID - DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id));// for byte mode, don't show value of another die. + + DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id)); p->vendor_id &= 0xFF; mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Vendor %x.\n", p->vendor_id)); - // Read MR6 for Revision ID - DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id));// for byte mode, don't show value of another die. + + DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id)); mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Revision %x.\n", p->revision_id)); - // Read MR6 for Revision ID2 - DramcModeRegReadByRank(p, RANK_0, 7, &u2MR7);// for byte mode, don't show value of another die. + + DramcModeRegReadByRank(p, RANK_0, 7, &u2MR7); mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Revision 2 %x.\n", u2MR7)); #if (!__ETT__) && (FOR_DV_SIMULATION_USED==0) set_dram_mr(5, p->vendor_id); @@ -1163,10 +1158,10 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf DramInfo->u8MR8Density[u1RankIdx] =0; } - // Read MR8 for dram density + for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++) { - #if 0//PRINT_CALIBRATION_SUMMARY + #if 0 if ((p->aru4CalExecuteFlag[u1ChannelIdx][u1RankIdx] != 0) && \ (p->aru4CalResultFlag[u1ChannelIdx][u1RankIdx] == 0)) #endif @@ -1179,7 +1174,7 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf u2MR8 |= (u2Density & 0xFF) << (u1RankIdx * 8); u1DieNumber = 1; - if (((u2Density >> 6) & 0x3) == 1) //OP[7:6] =0, x16 (normal mode) + if (((u2Density >> 6) & 0x3) == 1) u1DieNumber = 2; if (DramInfo != NULL) @@ -1189,33 +1184,33 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf switch (u2Density) { - ///TODO: Darren, please check the value of u8Size. + case 0x0: - u8Size = 0x20000000; //4Gb = 512MB + u8Size = 0x20000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 4Gb\n")); break; case 0x1: - u8Size = 0x30000000; //6Gb = 768MB + u8Size = 0x30000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 6Gb\n")); break; case 0x2: - u8Size = 0x40000000; //8Gb = 1GB = 2^30 bytes = 0x40000000 bytes + u8Size = 0x40000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 8Gb\n")); break; case 0x3: - u8Size = 0x60000000; //12Gb = 1.5GB = 3^30 bytes = 0x60000000 bytes + u8Size = 0x60000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 12Gb\n")); break; case 0x4: - u8Size = 0x80000000; //16Gb = 2GB = 4^30 bytes = 0x80000000 bytes + u8Size = 0x80000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 16Gb\n")); break; case 0x5: - u8Size = 0xc0000000; //24Gb = 3GB = 6^30 bytes = 0xc0000000 bytes + u8Size = 0xc0000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 24Gb\n")); break; case 0x6: - u8Size = 0x100000000L; //32Gb = 4GB = 8^30 bytes = 0x10000000 bytes + u8Size = 0x100000000L; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 32Gb\n")); break; default: @@ -1227,13 +1222,13 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf u8Size >>= 1; #endif - if (u8Size_backup < u8Size) // find max dram size for vDramcACTimingOptimize + if (u8Size_backup < u8Size) { u8Size_backup = u8Size; p->density = u2Density; } - p->ranksize[u1RankIdx] = u8Size * u1DieNumber; //dram rank size = density * DieNumber + p->ranksize[u1RankIdx] = u8Size * u1DieNumber; if (DramInfo != NULL) { @@ -1241,8 +1236,7 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf } } DramInfo->u4RankNum = p->support_rank_num; - // 1GB = 2^30 bytes - // u8Size * (2^3) / (2^30) ==>Gb + mcSHOW_DBG_MSG2(("RK%d, DieNum %d, Density %dGb, RKsize %dGb.\n\n", u1RankIdx, u1DieNumber, (U32)(u8Size >> 27), (U32)(p->ranksize[u1RankIdx] >> 27))); } #if (!__ETT__) && (FOR_DV_SIMULATION_USED==0) @@ -1262,8 +1256,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) TimeProfileBegin(); #endif -#if 0//SIMULATION_RX_INPUT_BUF // skip when bring up - //TODO: no shuffle, only need to do once under highest freq. +#if 0 if((p->frequency >= 2133) && (p->rank == RANK_0)) //if (p->rank == RANK_0) DramcRXInputBufferOffsetCal(p); @@ -1284,10 +1277,10 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) else u1RankMax = RANK_1; - //vAutoRefreshSwitch(p, DISABLE); //auto refresh is set as disable in LP4_DramcSetting, so don't need to disable again + //vAutoRefreshSwitch(p, DISABLE); vAutoRefreshSwitch(p, DISABLE); -#if 1//(SIMUILATION_CBT == 1) +#if 1 for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) { vSetRank(p, s1RankIdx); @@ -1301,7 +1294,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) if (GetEyeScanEnable(p, EYESCAN_TYPE_CBT) == ENABLE) { CmdBusTrainingLP45(p, AUTOK_OFF, EYESCAN_K); - print_EYESCAN_LOG_message(p, EYESCAN_TYPE_CBT); //draw CBT eyescan + print_EYESCAN_LOG_message(p, EYESCAN_TYPE_CBT); } #endif @@ -1317,23 +1310,22 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) No_Parking_On_CLRPLL(p); #endif - //@Darren, Fix high freq keep FSP0 for CA term workaround (PPR abnormal) - // The patch must to do after cbt training + ShuffleDfsToOriginalFSP(p); #endif -#if 0//(SIMULATION_WRITE_LEVELING == 1) +#if 0 for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) { vSetRank(p, s1RankIdx); - vAutoRefreshSwitch(p, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); #if (!WCK_LEVELING_FM_WORKAROUND) if (u1IsLP4Family(p->dram_type)) #endif { - if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) // skip for DDR800 rank1 + if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) { mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); @@ -1351,27 +1343,27 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) } vSetRank(p, RANK_0); - #if ENABLE_WDQS_MODE_2 // <=DDR1600 reduce PI change code time - if (!(u1IsLP4Div4DDR800(p)) && (p->frequency <= 800) && (p->support_rank_num == RANK_DUAL)) // skip DDR800semi, for DDR1200/DDR1600 only + #if ENABLE_WDQS_MODE_2 + if (!(u1IsLP4Div4DDR800(p)) && (p->frequency <= 800) && (p->support_rank_num == RANK_DUAL)) WriteLevelingPosCal(p, PI_BASED); - #elif ENABLE_TX_WDQS // for WDQS mode 1 to avoid dual rank PI code incorrect + #elif ENABLE_TX_WDQS if (!(u1IsLP4Div4DDR800(p)) && (p->support_rank_num == RANK_DUAL)) WriteLevelingPosCal(p, PI_BASED); #endif -#endif /* (SIMULATION_WRITE_LEVELING == 1) */ +#endif for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) { vSetRank(p, s1RankIdx); -#if 1//(SIMULATION_WRITE_LEVELING == 1) - vAutoRefreshSwitch(p, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable +#if 1 + vAutoRefreshSwitch(p, DISABLE); #if (!WCK_LEVELING_FM_WORKAROUND) if (u1IsLP4Family(p->dram_type)) #endif { - if ((!((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (p->rank == RANK_1))) // skip for DDR800 RANK1 + if ((!((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (p->rank == RANK_1))) && (!(vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE))) // skip for DDR400 { //mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); @@ -1387,13 +1379,13 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) TimeProfileBegin(); #endif } -#endif /* (SIMULATION_WRITE_LEVELING == 1) */ +#endif #if LJPLL_FREQ_DEBUG_LOG DDRPhyFreqMeter(p); #endif - vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable + vAutoRefreshSwitch(p, ENABLE); dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0); @@ -1407,7 +1399,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) DDRPhyFreqMeter(p); #endif -#if ENABLE_RX_INPUT_BUFF_OFF_K // skip when bring up +#if ENABLE_RX_INPUT_BUFF_OFF_K if((p->frequency >= 2133) && (p->rank == RANK_0)) DramcRXInputBufferOffsetCal(p); @@ -1449,7 +1441,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) #if TX_K_DQM_WITH_WDBI if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON)) { - // K DQM with DBI_ON, and check DQM window spec. + //mcSHOW_DBG_MSG(("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n")); vSwitchWriteDBISettings(p, DBI_ON); DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQM_ONLY, FALSE, AUTOK_OFF); @@ -1461,7 +1453,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) if (GetEyeScanEnable(p, EYESCAN_TYPE_TX) == ENABLE) { Dramc_K_TX_EyeScan_Log(p); - print_EYESCAN_LOG_message(p, EYESCAN_TYPE_TX); //draw TX eyescan + print_EYESCAN_LOG_message(p, EYESCAN_TYPE_TX); } #endif @@ -1491,7 +1483,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) CheckRxPinMux(p); #endif - DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, NORMAL_K); + DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, NORMAL_K); #ifdef DDR_INIT_TIME_PROFILING CPU_Cycle=TimeProfileEnd(); @@ -1503,8 +1495,8 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) #if ENABLE_EYESCAN_GRAPH if (GetEyeScanEnable(p, EYESCAN_TYPE_RX) == ENABLE) { - DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, EYESCAN_K); - print_EYESCAN_LOG_message(p, EYESCAN_TYPE_RX); //draw RX eyescan + DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, EYESCAN_K); + print_EYESCAN_LOG_message(p, EYESCAN_TYPE_RX); } #endif @@ -1534,7 +1526,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) if(p->femmc_Ready==0) #endif { - if(p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) // for 3733/4266 + if(p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) { U8 u1ByteIdx, u1HighFreqRXVref[2]; for(u1ByteIdx =0 ; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++) @@ -1552,7 +1544,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) } #endif - vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate()) + vSetRank(p, RANK_0); #if ENABLE_TX_TRACKING DramcDQSOSCShuSettings(p); @@ -1619,7 +1611,7 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p) CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL); for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) { - vSetPHY2ChannelMapping(p, channel_idx);// when switching channel, must update PHY to Channel Mapping + vSetPHY2ChannelMapping(p, channel_idx); CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL); vDramCalibrationSingleChannel(p); } @@ -1651,9 +1643,9 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p) } #endif - /* Enable/Disable calibrated rank's DBI function accordingly */ + #if ENABLE_READ_DBI - //Read DBI ON + vSetRank(p, RANK_0); vSetPHY2ChannelMapping(p, CHANNEL_A); @@ -1661,7 +1653,7 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p) #endif #if ENABLE_WRITE_DBI - // Just settle the DBI parameters which would be stored into shuffle space. + if (p->DBI_W_onoff[p->dram_fsp]) { for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) @@ -1671,13 +1663,13 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p) for (rank_idx = RANK_0; rank_idx < RANK_MAX; rank_idx++) { vSetRank(p, rank_idx); - DramcWriteShiftMCKForWriteDBI(p, -1); //Tx DQ/DQM -1 MCK for write DBI ON + DramcWriteShiftMCKForWriteDBI(p, -1); } vSetRank(p, RANK_0); } vSetPHY2ChannelMapping(p, CHANNEL_A); - // Improve Write DBI Power + ApplyWriteDBIPowerImprove(p, ENABLE); #if ENABLE_WRITE_DBI_Protect @@ -1782,7 +1774,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e p = &gTimeProfilingDramCtx; gfirst_init_flag = 0; - //DramcConfInfraReset(p); //No need when DDR_INIT_TIME_PROFILING_TEST_CNT=1 + //DramcConfInfraReset(p); #else p = psCurrDramCtx; #endif @@ -1793,7 +1785,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e p->dram_type = dram_type; - /* Convert DRAM_CBT_MODE_EXTERN_T to DRAM_CBT_MODE_T */ + switch ((int)dram_cbt_mode_extern) { case CBT_R0_R1_NORMAL: @@ -1835,7 +1827,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e while (1); #endif - DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); if (gfirst_init_flag == 0) { @@ -1855,7 +1847,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e backup_broadcast = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); mdl_setting(p); - UpdateGlobal10GBEnVariables(p); // @Darren, for 10GB + UpdateGlobal10GBEnVariables(p); TA2_Test_Run_Time_HW_Set_Column_Num(p); DramcBroadcastOnOff(backup_broadcast); } @@ -1867,26 +1859,25 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e vDramcInit_PreSettings(p); #endif - // DramC & PHY init for all channels - //=== First frequency ====== + #if defined(DUMP_INIT_RG_LOG_TO_DE) - vSetDFSFreqSelByTable(p, &gFreqTbl[1]); //0:3200 1:4266, 2:800, 3:1866, 4:1200, 5:2400, 6:1600 + vSetDFSFreqSelByTable(p, &gFreqTbl[1]); #else vSetDFSFreqSelByTable(p, &gFreqTbl[DRAM_DFS_SRAM_MAX-1]); //vSetDFSFreqSelByTable(p, &gFreqTbl[1]); #endif #if (DUAL_FREQ_K==0) || (__FLASH_TOOL_DA__) - gAndroid_DVFS_en = FALSE; //skip ETT DVFS stress + gAndroid_DVFS_en = FALSE; #endif #if RUNTIME_SHMOO_RELEATED_FUNCTION - ett_fix_freq = 1; /* only 1600 & 4266 */ + ett_fix_freq = 1; #endif if (!CONFIG(MEDIATEK_DRAM_DVFS)) - ett_fix_freq = 0x1; // 4266, 1600 + ett_fix_freq = 0x1; if (ett_fix_freq != 0xff) gAndroid_DVFS_en = FALSE; @@ -1895,14 +1886,13 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e DramcSave_Time_For_Cal_Init(p); #endif #ifndef LOOPBACK_TEST - if (p->dram_type == TYPE_LPDDR4X) // LP4/LP4P need confirm + if (p->dram_type == TYPE_LPDDR4X) { - // LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 - // LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 + DramcImpedanceCal(p, 1, IMP_LOW_FREQ); DramcImpedanceCal(p, 1, IMP_HIGH_FREQ); #if ENABLE_SAMSUNG_NT_ODT - DramcImpedanceCal(p, 1, IMP_NT_ODTN); // for Samsung NT ODTN + DramcImpedanceCal(p, 1, IMP_NT_ODTN); #endif } else @@ -1924,7 +1914,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e mcSHOW_DUMP_INIT_RG_MSG(("\n\n//=== DDR\033[1;32m%d\033[m\n",p->frequency<<1)); #endif - //Clk free run + //EnableDramcPhyDCM(p, 0); DFSInitForCalibration(p); @@ -1947,7 +1937,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e if (Get_MDL_Used_Flag()==GET_MDL_USED) { DramRankNumberDetection(p); - DFSInitForCalibration(p); // Restore setting after rank dection (especially DQ= DQS+16) + DFSInitForCalibration(p); } #endif @@ -1966,13 +1956,13 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e if (Get_MDL_Used_Flag()==GET_MDL_USED) { - // only K CHA to save time + vSetPHY2ChannelMapping(p, CHANNEL_A); - vCalibration_Flow_For_MDL(p); // currently for LP4 + vCalibration_Flow_For_MDL(p); GetDramInforAfterCalByMRR(p, DramInfo); return 0; } - else //NORMAL_USED + else { vDramCalibrationAllChannel(p); GetDramInforAfterCalByMRR(p, DramInfo); @@ -1990,7 +1980,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e #if SUPPORT_SAVE_TIME_FOR_CALIBRATION DramcSave_Time_For_Cal_End(p); #endif - LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); S8 u1ShuIdx; S8 s1ShuStart, s1ShuEnd; @@ -2028,7 +2018,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e DramcSave_Time_For_Cal_End(p); #endif } -#endif //(DUAL_FREQ_K) && (!__FLASH_TOOL_DA__) +#endif #ifdef DDR_INIT_TIME_PROFILING @@ -2043,7 +2033,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e #if __Petrus_TO_BE_PORTING__ -#if 0//TX_OE_CALIBATION, for DMA test +#if 0 U8 u1ChannelIdx, u1RankIdx; for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++) for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++) @@ -2073,13 +2063,13 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e DramcRegDump(p, SRAM_SHU0); #endif -// ETT_NO_DRAM #endif + #if ETT_NO_DRAM //NoDramDramcRegDump(p); NoDramRegFill(); #endif -#endif //#if __Petrus_TO_BE_PORTING__ +#endif #if DRAMC_MODEREG_CHECK DramcModeReg_Check(p); @@ -2104,22 +2094,22 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if (!(p->femmc_Ready == 0)) #elif defined(DDR_INIT_TIME_PROFILING) -if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of loop +if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) #endif #endif { EnableDFSHwModeClk(p); mcSHOW_DBG_MSG2(("DFS_SHUFFLE_HW_MODE: ON\n")); - if (gAndroid_DVFS_en == TRUE) // shuffle to DDR3733 boot + if (gAndroid_DVFS_en == TRUE) { #if defined(SLT) #ifdef SLT_2400_EXIT_PRELOADER - final_shu = SRAM_SHU0; //DDR2400 + final_shu = SRAM_SHU0; #else - final_shu = SRAM_SHU0; //DDR3200 + final_shu = SRAM_SHU0; #endif #else - final_shu = SRAM_SHU0; //DDR4266 + final_shu = SRAM_SHU0; #endif vSetDFSFreqSelByTable(p, get_FreqTbl_by_SRAMIndex(p, final_shu)); @@ -2135,7 +2125,7 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l #if __Petrus_TO_BE_PORTING__ #if (DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM && defined(DUMMY_READ_FOR_TRACKING)) - DramcDummyReadForSPMSideBand(p); // SPM dummy read 1us <-> 4us for DVT only (it must call after TransferPLLToSPMControl) + DramcDummyReadForSPMSideBand(p); #endif EnableDramcTrackingBySPMControl(p); @@ -2164,7 +2154,7 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l #if (__ETT__ && CPU_RW_TEST_AFTER_K) - /* 0x46000000 is LK base addr */ + //while(1) { //if ((s4value = dramc_complex_mem_test (0x46000000, 0x2000)) == 0) @@ -2190,9 +2180,9 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l #ifdef DDR_INIT_TIME_PROFILING CPU_Cycle = TimeProfileEnd(); mcSHOW_TIME_MSG((" (5) After calibration takes %d ms\n\r", CPU_Cycle / 1000)); -#endif // end of DDR_INIT_TIME_PROFILING +#endif -#endif//SW_CHANGE_FOR_SIMULATION +#endif #if defined(FOR_HQA_REPORT_USED) print_HQA_SLT_BIN_message(p); @@ -2212,21 +2202,21 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l return 0; } -///TODO: wait for porting --- + #if FOR_DV_SIMULATION_USED -///TODO: wait for porting +++ + void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t *psra) { U8 ii; - ///TODO: wait for porting +++ + #if GATING_ADJUST_TXDLY_FOR_TRACKING DramcRxdqsGatingPreProcess(DramConfig); #endif - ///TODO: wait for porting --- + vAutoRefreshSwitch(DramConfig, DISABLE); @@ -2239,7 +2229,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args mcSHOW_DBG_MSG6(("\n----->DramcCBT begin...\n")); timestamp_show(); #if CBT_O1_PINMUX_WORKAROUND - CmdBusTrainingLP45(DramConfig, AUTOK_OFF); //Cannot use aito-k in A60868 + CmdBusTrainingLP45(DramConfig, AUTOK_OFF); #else if (psra) CmdBusTrainingLP45(DramConfig, psra->cbt_autok, NORMAL_K); @@ -2254,7 +2244,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args { mcSHOW_DBG_MSG6(("CBT EYESCAN start<-----\n\n")); CmdBusTrainingLP45(DramConfig, AUTOK_OFF, EYESCAN_K); - print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_CBT); //draw CBT eyescan + print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_CBT); mcSHOW_DBG_MSG6(("CBT EYESCAN end<-----\n\n")); } #endif @@ -2264,25 +2254,25 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args ShuffleDfsToOriginalFSP(DramConfig); - ///TODO: wait for porting +++ + #if __A60868_TO_BE_PORTING__ No_Parking_On_CLRPLL(DramConfig); -#endif // __A60868_TO_BE_PORTING__ - ///TODO: wait for porting --- -#endif /* (SIMUILATION_CBT == 1) */ +#endif + +#endif for (ii = RANK_0; ii < DramConfig->support_rank_num; ii++) { vSetRank(DramConfig, ii); - vAutoRefreshSwitch(DramConfig, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable + vAutoRefreshSwitch(DramConfig, DISABLE); #if (SIMULATION_WRITE_LEVELING == 1) #if (!WCK_LEVELING_FM_WORKAROUND) if (u1IsLP4Family(DramConfig->dram_type)) #endif { - if (!(u1IsPhaseMode(DramConfig) && (DramConfig->rank == RANK_1))) // skip for DDR800 and DDR400 rank1 + if (!(u1IsPhaseMode(DramConfig) && (DramConfig->rank == RANK_1))) { if (!psra || psra->wl) { mcSHOW_DBG_MSG6(("\n----->DramcWriteLeveling(PI) begin...\n")); @@ -2299,7 +2289,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args } } } -#endif /* (SIMULATION_WRITE_LEVELING == 1) */ +#endif vAutoRefreshSwitch(DramConfig, ENABLE); @@ -2321,9 +2311,9 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args mcSHOW_DBG_MSG6(("\n----->DramcRxWindowPerbitCal RDDQC begin...\n")); timestamp_show(); - #if 0 // Used when testing LP5 RK1 WCK2CK in high efficiency mode and differential mode. + #if 0 p->rank = 1; - // For test HEFF = 1 / WCKDUAL = 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL), 0, SHU_WCKCTRL_WCKDUAL); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), P_Fld(1, SHU_COMMON0_LP5WCKON) | @@ -2335,7 +2325,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal end<-----\n\n")); } -#endif // (SIMULATION_RX_RDDQC == 1) +#endif #if (SIMULATION_TX_PERBIT == 1) if (!psra || psra->tx_perbit) { @@ -2369,15 +2359,15 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args { mcSHOW_DBG_MSG6(("\n----->DramcTxEYESCAN begin...\n")); Dramc_K_TX_EyeScan_Log(DramConfig); - print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_TX); //draw TX eyescan + print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_TX); mcSHOW_DBG_MSG6(("\n----->DramcTxEYESCAN end...\n")); } #endif } -#endif // (SIMULATION_TX_PERBIT == 1) +#endif #if (SIMULATION_DATLAT == 1) - if (1) { // No parameter in correspondence with by now + if (1) { mcSHOW_DBG_MSG6(("\n----->DramcRxdatlatCal begin...\n")); timestamp_show(); @@ -2386,7 +2376,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args timestamp_show(); mcSHOW_DBG_MSG6(("DramcRxdatlatCal end<-----\n\n")); } -#endif // (SIMULATION_DATLAT == 1) +#endif #if (SIMULATION_RX_PERBIT == 1) if (!psra || psra->rx_perbit) { @@ -2394,10 +2384,10 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args timestamp_show(); if (psra) DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, - NULL /*Set Vref = 0 to test*/, psra->rx_auto_cal, NORMAL_K); + NULL , psra->rx_auto_cal, NORMAL_K); else DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, - NULL /*Set Vref = 0 to test*/, AUTOK_OFF, NORMAL_K); + NULL , AUTOK_OFF, NORMAL_K); timestamp_show(); mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal end<-----\n\n")); @@ -2405,13 +2395,13 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args if (GetEyeScanEnable(DramConfig, EYESCAN_TYPE_RX) == ENABLE) { mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal EYESCAN start<-----\n\n")); - DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, EYESCAN_K); - print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_RX); //draw RX eyescan + DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, EYESCAN_K); + print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_RX); mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal EYESCAN end<-----\n\n")); } #endif } -#endif // (SIMULATION_RX_PERBIT == 1) +#endif #if (SIMULATION_RX_DVS == 1) if (DramConfig->frequency >=2133) @@ -2423,10 +2413,10 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args { DramcTxOECalibration(DramConfig); } -#endif // TX_OE_CALIBATION +#endif #if ENABLE_TX_TRACKING - #if 0 /* Starting from Vinson, no need to pre-calculate MR23 for different freqs */ + #if 0 if (gu1MR23Done == FALSE) { DramcDQSOSCAuto(p); @@ -2444,7 +2434,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args DramcDQSOSCShuSettings(DramConfig); #endif -///TODO: wait for porting +++ + #if GATING_ADJUST_TXDLY_FOR_TRACKING DramcRxdqsGatingPostProcess(DramConfig); #endif @@ -2474,7 +2464,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args RDSELRunTimeTracking_preset(DramConfig); #endif -///TODO: wait for porting --- + } @@ -2485,20 +2475,20 @@ void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t CKEFixOnOff(DramConfig, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL); for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++) { - vSetPHY2ChannelMapping(DramConfig, channel_idx);// when switching channel, must update PHY to Channel Mapping + vSetPHY2ChannelMapping(DramConfig, channel_idx); CKEFixOnOff(DramConfig, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL); DPI_vDramCalibrationSingleChannel(DramConfig, psra); } vSetPHY2ChannelMapping(DramConfig, CHANNEL_A); -///TODO: wait for porting +++ + #if ENABLE_READ_DBI DramcReadDBIOnOff(DramConfig, DramConfig->DBI_R_onoff[DramConfig->dram_fsp]); #endif #if ENABLE_WRITE_DBI - // Just settle the DBI parameters which would be stored into shuffle space. + if (DramConfig->DBI_W_onoff[DramConfig->dram_fsp]) { for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++) @@ -2508,13 +2498,13 @@ void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t for (rank_idx = RANK_0; rank_idx < DramConfig->support_rank_num; rank_idx++) { vSetRank(DramConfig, rank_idx); - DramcWriteShiftMCKForWriteDBI(DramConfig, -1); //Tx DQ/DQM -1 MCK for write DBI ON + DramcWriteShiftMCKForWriteDBI(DramConfig, -1); } vSetRank(DramConfig, RANK_0); } vSetPHY2ChannelMapping(DramConfig, CHANNEL_A); - // Improve Write DBI Power + ApplyWriteDBIPowerImprove(DramConfig, ENABLE); #if ENABLE_WRITE_DBI_Protect @@ -2559,11 +2549,11 @@ void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t mcSHOW_DBG_MSG6(("TX_TRACKING: OFF\n")); #endif -///TODO: wait for porting --- + } -///TODO: wait for porting +++ + #if __A60868_TO_BE_PORTING__ void RG_dummy_write(DRAMC_CTX_T *p, U32 pattern) { @@ -2574,10 +2564,10 @@ void RG_dummy_write(DRAMC_CTX_T *p, U32 pattern) void EnablePLLtoSPMControl(DRAMC_CTX_T *p) { - vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL); // DFS SPM mode for calibration + vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL); } -#endif // __A60868_TO_BE_PORTING__ -///TODO: wait for porting --- +#endif + void dump_dramc_ctx(DRAMC_CTX_T *p) { @@ -2614,7 +2604,7 @@ void DPI_SW_main_LP4(DRAMC_CTX_T *ExtConfig, cal_sv_rand_args_t *psra) S8 s1ShuIdx; #endif - DRAMC_CTX_T *p = &DramCtx_LPDDR4; //default; + DRAMC_CTX_T *p = &DramCtx_LPDDR4; p->dram_type = ExtConfig->dram_type; if(p->dram_type==TYPE_LPDDR5) @@ -2633,15 +2623,15 @@ void DPI_SW_main_LP4(DRAMC_CTX_T *ExtConfig, cal_sv_rand_args_t *psra) p->freqGroup = ExtConfig->freqGroup; p->new_cbt_mode = ExtConfig->new_cbt_mode; -#if 0 // for Refs +#if 0 DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { - {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. - {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. - {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) - {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, + {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, + {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, + {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, }; #endif if (u1IsLP4Family(p->dram_type)) @@ -2669,36 +2659,34 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { enter_function(); if (!psra) { - /* - * for SA's simulation - */ + mcSHOW_DBG_MSG6(("enter SA's simulation flow.\n")); p->support_channel_num = CHANNEL_SINGLE; p->channel = CHANNEL_A; p->support_rank_num = RANK_DUAL; - /* DramRank */ + p->rank = RANK_0; - /* DRAMC operation clock frequency in MHz */ + #if (fcFOR_CHIP_ID == fcA60868) #if DV_SIMULATION_DFS p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX-1]; #endif #endif #if 0 - /* DRAM type */ + #if DV_SIMULATION_LP4 p->dram_type = TYPE_LPDDR4X; - //p->freq_sel = LP4_DDR3200;//DV_SIMULATION_RUN_FREQ_SEL; - //p->frequency = 1600;//DV_SIMULATION_RUN_FREQ; - p->freq_sel = LP4_DDR1600;//DV_SIMULATION_RUN_FREQ_SEL; - p->frequency = 800;//DV_SIMULATION_RUN_FREQ; + //p->freq_sel = LP4_DDR3200; + //p->frequency = 1600; + p->freq_sel = LP4_DDR1600; + p->frequency = 800; #else p->dram_type = TYPE_LPDDR5; - p->freq_sel = LP5_DDR3200;//DV_SIMULATION_RUN_FREQ_SEL; - p->frequency = 1600;//DV_SIMULATION_RUN_FREQ; + p->freq_sel = LP5_DDR3200; + p->frequency = 1600; #endif #endif - /* DRAM Fast switch point type, only for LP4, useless in LP3 */ + p->dram_fsp = FSP_0; #if 0 @@ -2710,31 +2698,31 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; #endif #endif - /* IC and DRAM read DBI */ - p->DBI_R_onoff[FSP_0] = DBI_OFF; /* only for LP4, uesless in LP3 */ - p->DBI_R_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + + p->DBI_R_onoff[FSP_0] = DBI_OFF; + p->DBI_R_onoff[FSP_1] = DBI_OFF; #if ENABLE_READ_DBI - p->DBI_R_onoff[FSP_1] = DBI_ON; /* only for LP4, uesless in LP3 */ + p->DBI_R_onoff[FSP_1] = DBI_ON; #else - p->DBI_R_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + p->DBI_R_onoff[FSP_1] = DBI_OFF; #endif - /* IC and DRAM write DBI */ - p->DBI_W_onoff[FSP_0] = DBI_OFF; /* only for LP4, uesless in LP3 */ - p->DBI_W_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + + p->DBI_W_onoff[FSP_0] = DBI_OFF; + p->DBI_W_onoff[FSP_1] = DBI_OFF; #if ENABLE_WRITE_DBI - p->DBI_W_onoff[FSP_1] = DBI_ON; /* only for LP4, uesless in LP3 */ + p->DBI_W_onoff[FSP_1] = DBI_ON; #else - p->DBI_W_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + p->DBI_W_onoff[FSP_1] = DBI_OFF; #endif - /* bus width */ + p->data_width = DATA_WIDTH_16BIT; - /* DRAMC internal test engine-2 parameters in calibration */ + p->test2_1 = DEFAULT_TEST2_1_CAL; p->test2_2 = DEFAULT_TEST2_2_CAL; - /* DRAMC test pattern in calibration */ + p->test_pattern = TEST_XTALK_PATTERN; - /* u2DelayCellTimex100 */ - p->u2DelayCellTimex100 = 250; // @Darren, 2.5ps + + p->u2DelayCellTimex100 = 250; p->vendor_id = 0x1; p->density = 0; /* p->ranksize = {0,0}; */ @@ -2751,50 +2739,48 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { p->lp5_cbt_phase = CBT_PHASE_FALLING; #endif } else { - /* - * for DV's regression - */ + mcSHOW_DBG_MSG6(("enter DV's regression flow.\n")); p->support_channel_num = CHANNEL_SINGLE; p->channel = psra->calibration_channel; p->support_rank_num = RANK_DUAL; - /* DramRank */ + p->rank = psra->calibration_rank; - /* DRAMC operation clock frequency in MHz */ + #if (fcFOR_CHIP_ID == fcA60868) #if DV_SIMULATION_DFS p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX-1]; #endif #endif - /* DRAM type */ + //p->dram_type = psra->dram_type; - //p->freq_sel = LP5_DDR4266;//DV_SIMULATION_RUN_FREQ_SEL; - //p->frequency = 2133;//DV_SIMULATION_RUN_FREQ; + //p->freq_sel = LP5_DDR4266; + //p->frequency = 2133; set_type_freq_by_svargs(p, psra); - /* DRAM Fast switch point type, only for LP4, useless in LP3 */ + p->dram_fsp = FSP_0; p->dram_cbt_mode[RANK_0] = psra->rk0_cbt_mode; p->dram_cbt_mode[RANK_1] = psra->rk1_cbt_mode; - /* IC and DRAM read DBI */ - p->DBI_R_onoff[FSP_0] = (psra->mr3_value >> 6) & 0x1; /* only for LP4, uesless in LP3 */ - p->DBI_R_onoff[FSP_1] = (psra->mr3_value >> 6) & 0x1; /* only for LP4, uesless in LP3 */ + + p->DBI_R_onoff[FSP_0] = (psra->mr3_value >> 6) & 0x1; + p->DBI_R_onoff[FSP_1] = (psra->mr3_value >> 6) & 0x1; p->DBI_R_onoff[FSP_2] = (psra->mr3_value >> 6) & 0x1; - /* IC and DRAM write DBI */ - p->DBI_W_onoff[FSP_0] = (psra->mr3_value >> 7) & 0x1; /* only for LP4, uesless in LP3 */ - p->DBI_W_onoff[FSP_1] = (psra->mr3_value >> 7) & 0x1; /* only for LP4, uesless in LP3 */ + + p->DBI_W_onoff[FSP_0] = (psra->mr3_value >> 7) & 0x1; + p->DBI_W_onoff[FSP_1] = (psra->mr3_value >> 7) & 0x1; p->DBI_W_onoff[FSP_2] = (psra->mr3_value >> 7) & 0x1; - /* bus width */ + p->data_width = DATA_WIDTH_16BIT; - /* DRAMC internal test engine-2 parameters in calibration */ + p->test2_1 = DEFAULT_TEST2_1_CAL; p->test2_2 = DEFAULT_TEST2_2_CAL; - /* DRAMC test pattern in calibration */ + p->test_pattern = TEST_XTALK_PATTERN; - /* u2DelayCellTimex100 */ + p->u2DelayCellTimex100 = 0; p->vendor_id = 0x1; p->density = 0; @@ -2815,8 +2801,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { p->dram_fsp = (psra->mr13_value >> 7) & 0x1; } -// p->dram_type = TYPE_LPDDR5; -// #define __FW_VER__ "WCK leveling with DLY +16! and MRinit for FSP1 -- 777" + #define __FW_VER__ "All struct move done, new RX range -- 444" if (u1IsLP4Family(p->dram_type)) { @@ -2859,7 +2844,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { value = u4Dram_Register_Read(p, DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL ); mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL, value)); - DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); Global_Option_Init(p); @@ -2869,15 +2854,14 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { DDRPhyFreqSel(p, p->pDFSTable->freq_sel); vSetPHY2ChannelMapping(p, p->channel); -#endif // __A60868_TO_BE_PORTING__ - ///TODO: wait for porting --- +#endif if (u1IsLP4Family(p->dram_type)) { - vSetDFSFreqSelByTable(p, p->pDFSTable); // for LP4x + vSetDFSFreqSelByTable(p, p->pDFSTable); } - else ///TODO: Jeremy, modify this when LP5 gFreqtbl ready + else { DDRPhyFreqSel(p, p->freq_sel); } @@ -2885,19 +2869,18 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { #if (SIMULATION_SW_IMPED == 1) mcSHOW_DBG_MSG6(("\n----->DramcImpedanceCal begin...\n")); timestamp_show(); - // LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 - // LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 + DramcImpedanceCal(p, 1, IMP_LOW_FREQ); DramcImpedanceCal(p, 1, IMP_HIGH_FREQ); timestamp_show(); mcSHOW_DBG_MSG6(("DramcImpedanceCal end<-----\n\n")); -#endif /* (SIMULATION_SW_IMPED == 1) */ +#endif #if DV_SIMULATION_INIT_C - ///TODO: wait for porting +++ + DramcInit(p); - // Before calibration setting + vBeforeCalibration(p); #if __A60868_TO_BE_PORTING__ #if DV_SIMULATION_BEFORE_K @@ -2906,15 +2889,14 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { #endif #ifdef DUMP_INIT_RG_LOG_TO_DE - #if 0 //Dump RG to other shuffle for FT used, don't delete + #if 0 mcSHOW_DUMP_INIT_RG_MSG(("\n\n\n\n\n\n===== Save to Shuffle RG ======\n")); DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3); #endif while (1); #endif #endif -#endif // __A60868_TO_BE_PORTING__ - ///TODO: wait for porting --- +#endif #if (SIMULATION_MIOCK_JMETER == 1) @@ -2923,26 +2905,24 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { p->u2DelayCellTimex100 = GetVcoreDelayCellTime(p); timestamp_show(); mcSHOW_DBG_MSG6(("DramcMiockJmeter end<-----\n\n")); -#endif /* (SIMULATION_MIOCK_JMETER == 1) */ +#endif #if (SIMULATION_8PHASE == 1) if(is_lp5_family(p) && (p->frequency >= 2133)) { mcSHOW_DBG_MSG6(("\n----->Dramc8PhaseCal begin...\n")); timestamp_show(); - Dramc8PhaseCal(p); // it must set before duty calib + Dramc8PhaseCal(p); timestamp_show(); mcSHOW_DBG_MSG6(("Dramc8PhaseCal end<-----\n\n")); } -#endif /* (SIMULATION_8PHASE == 1) */ - - ///TODO: wait for porting +++ - #if !DV_SIMULATION_DFS // No calib will use legacy mode init settings - DPI_vDramCalibrationAllChannel(p, psra); // for DDR1600 1:8 mode +#endif + #if !DV_SIMULATION_DFS + DPI_vDramCalibrationAllChannel(p, psra); #endif #if DV_SIMULATION_DFS DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, vGet_Current_SRAMIdx(p)); - LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); #if (fcFOR_CHIP_ID == fcA60868) for (s1ShuIdx = DRAM_DFS_SRAM_MAX - 10; s1ShuIdx >= 0; s1ShuIdx--) @@ -2952,7 +2932,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { { vSetDFSFreqSelByTable(p, &gFreqTbl[s1ShuIdx]); DramcInit(p); - // Before calibration setting + vBeforeCalibration(p); #if DV_SIMULATION_BEFORE_K @@ -2963,31 +2943,31 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { if(is_lp5_family(p) && (p->frequency >= 2133)) { mcSHOW_DBG_MSG6(("\n----->Dramc8PhaseCal begin...\n")); timestamp_show(); - Dramc8PhaseCal(p); // it must set before duty calib + Dramc8PhaseCal(p); timestamp_show(); mcSHOW_DBG_MSG6(("Dramc8PhaseCal end<-----\n\n")); } - #endif /* (SIMULATION_8PHASE == 1) */ + #endif - #if !DV_SIMULATION_DFS // No calib will use legacy mode init settings - DPI_vDramCalibrationAllChannel(p, psra); // for gDVDFSTbl + #if !DV_SIMULATION_DFS + DPI_vDramCalibrationAllChannel(p, psra); #endif DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, gFreqTbl[s1ShuIdx].SRAMIdx); } #endif - ///TODO: wait for porting --- - ///TODO: wait for porting +++ + + vAfterCalibration(p); #if SIMULATION_RUNTIME_CONFIG DramcRunTimeConfig(p); #endif -#if 0//__A60868_TO_BE_PORTING__ +#if 0 #if DV_SIMULATION_AFTER_K vApplyConfigAfterCalibration(p); #endif @@ -3003,11 +2983,10 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { mcSHOW_DBG_MSG(("[Runtime time MRR] MR4 = 0x%x, MR5 = 0x%x, MR8 = 0x%x\n", u2val1, u2val2, u2val3)); #endif -#if 0//DV_SIMULATION_DFS // NOTE: Don't use DramcDFSDirectJump_SPMMode. it will cause NULL object access. - // high freq -> low freq +#if 0 for (s1ShuIdx = 0; s1ShuIdx < DV_SIMULATION_DFS_SHU_MAX; s1ShuIdx++) DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].SRAMIdx); - // low freq -> high freq + for (s1ShuIdx = DV_SIMULATION_DFS_SHU_MAX - 1; s1ShuIdx >= DRAM_DFS_SHUFFLE_1; s1ShuIdx--) DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].SRAMIdx); #endif @@ -3017,8 +2996,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { #endif RG_dummy_write(p, 0xAAAAAAAA); -#endif // __A60868_TO_BE_PORTING__ - ///TODO: wait for porting --- +#endif //Temp_TA2_Test_After_K(p); @@ -3033,9 +3011,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { exit_function(); } -/* - * start_dramk -- c calibration entry for SA's simulation - */ + void start_dramk(void) { DRAMC_CTX_T *p; @@ -3047,11 +3023,7 @@ void start_dramk(void) exit_function(); } -/* - * sa_calibration -- c calibration entry for DV's regression - * - * @psra: random arguments from sv to c for calibration controlling - */ + void sa_calibration(cal_sv_rand_args_t *psra) { DRAMC_CTX_T *p; @@ -3083,7 +3055,7 @@ out: } -///TODO: wait for porting +++ + #if __A60868_TO_BE_PORTING__ #if SW_CHANGE_FOR_SIMULATION void main(void) @@ -3092,37 +3064,37 @@ void main(void) DRAMC_CTX_T DramConfig; DramConfig.channel = CHANNEL_A; DramConfig.support_rank_num = RANK_DUAL; - // DramRank + DramConfig.rank = RANK_0; - // DRAM type + DramConfig.dram_type = TYPE_LPDDR4X; - // DRAM Fast switch point type, only for LP4, useless in LP3 + DramConfig.dram_fsp = FSP_0; - // DRAM CBT mode, only for LP4, useless in LP3 + DramConfig.dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; DramConfig.dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; - // IC and DRAM read DBI - DramConfig.DBI_R_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3 + + DramConfig.DBI_R_onoff[FSP_0] = DBI_OFF; #if ENABLE_READ_DBI - DramConfig.DBI_R_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3 + DramConfig.DBI_R_onoff[FSP_1] = DBI_ON; #else - DramConfig.DBI_R_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3 + DramConfig.DBI_R_onoff[FSP_1] = DBI_OFF; #endif - // IC and DRAM write DBI - DramConfig.DBI_W_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3 + + DramConfig.DBI_W_onoff[FSP_0] = DBI_OFF; #if ENABLE_WRITE_DBI - DramConfig.DBI_W_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3 + DramConfig.DBI_W_onoff[FSP_1] = DBI_ON; #else - DramConfig.DBI_W_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3 + DramConfig.DBI_W_onoff[FSP_1] = DBI_OFF; #endif - // bus width + DramConfig.data_width = DATA_WIDTH_32BIT; - // DRAMC internal test engine-2 parameters in calibration + DramConfig.test2_1 = DEFAULT_TEST2_1_CAL; DramConfig.test2_2 = DEFAULT_TEST2_2_CAL; - // DRAMC test pattern in calibration + DramConfig.test_pattern = TEST_XTALK_PATTERN; - // DRAMC operation clock frequency in MHz + DramConfig.frequency = 800; //DramConfig.enable_rx_scan_vref =DISABLE; @@ -3133,7 +3105,7 @@ void main(void) Global_Option_Init(&DramConfig); - // DramC & PHY init for all channels + DDRPhyFreqSel(&DramConfig, LP4_DDR1600); @@ -3150,8 +3122,8 @@ void main(void) vSetPHY2ChannelMapping(&DramConfig, DramConfig.channel); #if SIMULATION_SW_IMPED - DramcImpedanceCal(&DramConfig, 1, LOW_FREQ); //for DRVN/P and ODTN - //DramcImpedanceCal(&DramConfig, 1, HIGH_FREQ); //for DRVN/P and ODTN + DramcImpedanceCal(&DramConfig, 1, LOW_FREQ); + //DramcImpedanceCal(&DramConfig, 1, HIGH_FREQ); #endif @@ -3171,10 +3143,10 @@ void main(void) #endif #if SIMULATION_GATING - // Gating calibration of single rank + DramcRxdqsGatingCal(&DramConfig); - // Gating calibration of both rank + //DualRankDramcRxdqsGatingCal(&DramConfig); #endif @@ -3183,10 +3155,10 @@ void main(void) #endif #if SIMULATION_DATLAT - // RX Datlat calibration of single rank + DramcRxdatlatCal(&DramConfig); - // RX Datlat calibration of two rank + //DramcDualRankRxdatlatCal(&DramConfig); #endif @@ -3200,12 +3172,12 @@ void main(void) #endif #if ENABLE_READ_DBI - //Read DBI ON + SetDramModeRegForReadDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_R_onoff[DramConfig.dram_fsp]); #endif #if ENABLE_WRITE_DBI - //Write DBI ON + DramcWriteShiftMCKForWriteDBI(&DramConfig, -1); SetDramModeRegForWriteDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]); #endif @@ -3218,8 +3190,7 @@ void main(void) DramcWriteDBIOnOff(&DramConfig, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]); #endif } -#endif //SW_CHANGE_FOR_SIMULATION -#endif // __A60868_TO_BE_PORTING__ -///TODO: wait for porting --- +#endif +#endif #endif |