diff options
Diffstat (limited to 'src')
95 files changed, 1569 insertions, 745 deletions
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index fd61cab44d8e..acd26a41be95 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/x86/gdt.h> #include <cpu/x86/post_code.h> -#include <arch/ram_segs.h> /* Place the stack in the bss section. It's not necessary to define it in * the linker script. */ @@ -30,9 +30,9 @@ _start: lgdt (%rax) #else lgdt %cs:gdtaddr - ljmp $RAM_CODE_SEG, $1f + ljmp $GDT_CODE_SEG, $1f #endif -1: movl $RAM_DATA_SEG, %eax +1: movl $GDT_DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss @@ -40,7 +40,7 @@ _start: movl %eax, %fs movl %eax, %gs /* Will be used for cpu_info */ #if ENV_X86_64 - mov $RAM_CODE_SEG64, %ecx + mov $GDT_CODE_SEG64, %ecx call SetCodeSelector #endif @@ -152,46 +152,44 @@ gdtaddr: .data - /* This is the gdt for GCC part of coreboot. + /* + * This is the gdt for coreboot's ramstage. * It is different from the gdt in ASM part of coreboot * which is defined in gdt_init.S * * When the machine is initially started, we use a very simple * gdt from ROM (that in gdt_init.S) which only contains those - * entries we need for protected mode. + * entries we need for protected mode and long mode. * * When we're executing code from RAM, we want to do more complex * stuff, like initializing PCI option ROMs in real mode, or doing - * a resume from a suspend to RAM. + * a resume from a suspend to RAM, which happens in real mode. + * + * Keep in sync with 'cpu/x86/gdt.h'. */ gdt: /* selgdt 0, unused */ .word 0x0000, 0x0000 /* dummy */ .byte 0x00, 0x00, 0x00, 0x00 - /* selgdt 8, unused */ - .word 0x0000, 0x0000 /* dummy */ - .byte 0x00, 0x00, 0x00, 0x00 - - /* selgdt 0x10, flat code segment */ + /* selgdt 0x08, flat code segment */ .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for - * limit - */ + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes + for limit */ - /* selgdt 0x18, flat data segment */ + /* selgdt 0x10, flat data segment */ .word 0xffff, 0x0000 -#if ENV_X86_64 - .byte 0x00, 0x92, 0xcf, 0x00 -#else .byte 0x00, 0x93, 0xcf, 0x00 -#endif - /* selgdt 0x20, unused */ - .word 0x0000, 0x0000 /* dummy */ - .byte 0x00, 0x00, 0x00, 0x00 + /* selgdt 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 + + /* gdt selector 0x20 tss segment, used by STM */ + .word 0xffff, 0x0000 + .byte 0x00, 0x8b, 0x80, 0x00 - /* The next two entries are used for executing VGA option ROMs */ + /* The next two entries are used for executing ACPI S3 RESUME and VGA option ROMs */ /* selgdt 0x28 16 bit 64k code at 0x00000000 */ .word 0xffff, 0x0000 @@ -201,34 +199,25 @@ gdt: .word 0xffff, 0x0000 .byte 0, 0x92, 0, 0 - /* The next two entries are used for ACPI S3 RESUME */ + /* The next entry is used for VGA option ROMs. See x86_asm.S */ - /* selgdt 0x38, flat data segment 16 bit */ - .word 0x0000, 0x0000 /* dummy */ - .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for - * limit - */ - - /* selgdt 0x40, flat code segment 16 bit */ + /* + * selgdt 0x38, flat code segment 16 bits + * + * FIXME: It's only used in %ds (therefore used like a data segment). + * The PCI Specification doesn't enforce this. + * Is this a workaround for broken Option ROMs? + */ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for * limit */ -#if ENV_X86_64 - /* selgdt 0x48, flat x64 code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xaf, 0x00 -#endif per_cpu_segment_descriptors: .rept CONFIG_MAX_CPUS /* flat data segment */ .word 0xffff, 0x0000 -#if ENV_X86_64 - .byte 0x00, 0x92, 0xcf, 0x00 -#else .byte 0x00, 0x93, 0xcf, 0x00 -#endif .endr gdt_end: diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 224f0e1d4164..e21cfa6de583 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -665,6 +665,8 @@ asmlinkage void exception_init(void) load_idt(idt, sizeof(idt)); +#if !ENV_SMM null_breakpoint_init(); stack_canary_breakpoint_init(); +#endif } diff --git a/src/arch/x86/include/arch/ram_segs.h b/src/arch/x86/include/arch/ram_segs.h deleted file mode 100644 index 3f92a1f6803a..000000000000 --- a/src/arch/x86/include/arch/ram_segs.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef RAM_SEGS_H -#define RAM_SEGS_H - -#define RAM_CODE_SEG 0x10 -#define RAM_DATA_SEG 0x18 -#define RAM_CODE16_SEG 0x28 -#define RAM_DATA16_SEG 0x30 -#define RAM_CODE_ACPI_SEG 0x38 -#define RAM_DATA_ACPI_SEG 0x40 -#define RAM_CODE_SEG64 0x48 - -#endif /* RAM_SEGS_H */ diff --git a/src/arch/x86/include/arch/rom_segs.h b/src/arch/x86/include/arch/rom_segs.h deleted file mode 100644 index a7e31d29511d..000000000000 --- a/src/arch/x86/include/arch/rom_segs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef ROM_SEGS_H -#define ROM_SEGS_H - -#define ROM_CODE_SEG 0x08 -#define ROM_DATA_SEG 0x10 -#define ROM_CODE_SEG64 0x18 - -/* - * This define is placed here to make sure future romstage programmers - * know about it. - * It is used for STM setup code. - */ -#define SMM_TASK_STATE_SEG 0x20 - -#endif /* ROM_SEGS_H */ diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index 7bff006d14bc..1afc31173553 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/ram_segs.h> +#include <cpu/x86/gdt.h> #define WAKEUP_BASE 0x600 #define RELOCATED(x) (x - __wakeup + WAKEUP_BASE) @@ -31,7 +31,7 @@ __wakeup: add $8, %rax push %rax pushfq - push $RAM_CODE_SEG + push $GDT_CODE_SEG lea 3(%rip), %rax push %rax iretq @@ -60,7 +60,7 @@ __wakeup: movw %ax, (__wakeup_segment) /* Activate the right segment descriptor real mode. */ - ljmp $RAM_CODE16_SEG, $RELOCATED(1f) + ljmp $GDT_CODE16_SEG, $RELOCATED(1f) 1: .code16 /* 16 bit code from here on... */ @@ -70,7 +70,7 @@ __wakeup: * configurations (limits, writability, etc.) once * protected mode is turned off. */ - mov $RAM_DATA16_SEG, %ax + mov $GDT_DATA16_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 78dbe8ef4c51..7860a413ce07 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -539,11 +539,17 @@ struct lb_smmstorev2 { uint32_t size; uint32_t num_blocks; /* Number of writable blocks in SMM */ uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ - uint32_t mmap_addr; /* MMIO address of the store for read only access */ + uint32_t mmap_addr_deprecated; /* 32-bit MMIO address of the store for read only access. + Prefer 'mmap_addr' for new software. + Zero when the address won't fit into 32-bits. */ uint32_t com_buffer; /* Physical address of the communication buffer */ uint32_t com_buffer_size; /* Size of the communication buffer in bytes */ uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ uint8_t unused[3]; /* Set to zero */ + uint64_t mmap_addr; /* 64-bit MMIO address of the store for read only access. + Introduced after the initial implementation. Users of + this table must check the 'size' field to detect if its + written out by coreboot. */ }; enum lb_tpm_ppi_tpm_version { diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 52da6037d554..a9f7ba49a8e2 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -17,12 +17,8 @@ #endif #endif +#include <cpu/x86/gdt.h> #include <cpu/x86/msr.h> -#if defined(__RAMSTAGE__) -#include <arch/ram_segs.h> -#else -#include <arch/rom_segs.h> -#endif .macro setup_longmode page_table /* Get page table address */ @@ -48,12 +44,8 @@ movl %eax, %cr0 /* use long jump to switch to 64-bit code segment */ -#if defined(__RAMSTAGE__) - ljmp $RAM_CODE_SEG64, $jmp_addr\@ -#else - ljmp $ROM_CODE_SEG64, $jmp_addr\@ + ljmp $GDT_CODE_SEG64, $jmp_addr\@ -#endif .code64 jmp_addr\@: .endm diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 3ac86a9df101..a3d215e785b6 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -10,17 +10,9 @@ */ .code64 +#include <cpu/x86/gdt.h> #include <cpu/x86/msr.h> #include <cpu/x86/cr.h> -#if defined(__RAMSTAGE__) -#include <arch/ram_segs.h> -#define CODE_SEG RAM_CODE_SEG -#define DATA_SEG RAM_DATA_SEG -#else -#include <arch/rom_segs.h> -#define CODE_SEG ROM_CODE_SEG -#define DATA_SEG ROM_DATA_SEG -#endif drop_longmode: #if !ENV_CACHE_AS_RAM @@ -28,7 +20,7 @@ drop_longmode: wbinvd #endif /* Set 32-bit code segment and ss */ - mov $CODE_SEG, %rcx + mov $GDT_CODE_SEG, %rcx /* SetCodeSelector32 will drop us to protected mode on return */ call SetCodeSelector32 @@ -63,7 +55,7 @@ __longmode_compatibility: /* Running in 32-bit compatibility mode */ /* Use flat data segment */ - movl $DATA_SEG, %eax + movl $GDT_DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss diff --git a/src/cpu/x86/entry16.S b/src/cpu/x86/entry16.S index ff4f1a26d04f..b19ffa5d6aff 100644 --- a/src/cpu/x86/entry16.S +++ b/src/cpu/x86/entry16.S @@ -27,7 +27,7 @@ /* Start code to put an i386 or later processor into 32-bit protected mode. */ -#include <arch/rom_segs.h> +#include <cpu/x86/gdt.h> #include <cpu/x86/post_code.h> .section .init._start, "ax", @progbits @@ -136,7 +136,7 @@ _start16bit: movl %ebp, %eax /* Now that we are in protected mode jump to a 32 bit code segment. */ - ljmpl $ROM_CODE_SEG, $bootblock_protected_mode_entry + ljmpl $GDT_CODE_SEG, $bootblock_protected_mode_entry /** * The gdt is defined in gdt_init.S, it has a 4 Gb code segment diff --git a/src/cpu/x86/entry32.S b/src/cpu/x86/entry32.S index 5c29581090a8..d013cbaf602a 100644 --- a/src/cpu/x86/entry32.S +++ b/src/cpu/x86/entry32.S @@ -11,7 +11,7 @@ * */ -#include <arch/rom_segs.h> +#include <cpu/x86/gdt.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> @@ -33,7 +33,7 @@ bootblock_protected_mode_entry: post_code(POSTCODE_ENTER_PROTECTED_MODE) - movw $ROM_DATA_SEG, %ax + movw $GDT_DATA_SEG, %ax movw %ax, %ds movw %ax, %es movw %ax, %ss diff --git a/src/cpu/x86/mtrr/Makefile.mk b/src/cpu/x86/mtrr/Makefile.mk index c74f014531d5..2846280d258f 100644 --- a/src/cpu/x86/mtrr/Makefile.mk +++ b/src/cpu/x86/mtrr/Makefile.mk @@ -1,5 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-y += mtrrlib.c +verstage_x86-y += mtrrlib.c +romstage-y += mtrrlib.c +postcar-y += mtrrlib.c +ramstage-y += mtrrlib.c + ramstage-y += mtrr.c romstage-y += earlymtrr.c diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 6c819a8c46f3..4ca7a0a5a4dc 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -7,67 +7,14 @@ #include <commonlib/bsd/helpers.h> #include <types.h> -/* Get first available variable MTRR. - * Returns var# if available, else returns -1. - */ -int get_free_var_mtrr(void) -{ - msr_t maskm; - int vcnt; - int i; - - vcnt = get_var_mtrr_count(); - - /* Identify the first var mtrr which is not valid. */ - for (i = 0; i < vcnt; i++) { - maskm = rdmsr(MTRR_PHYS_MASK(i)); - if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0) - return i; - } - - /* No free var mtrr. */ - return -1; -} - -void set_var_mtrr( - unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) -{ - /* Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - - if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM) - printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n", - type); - if (!IS_POWER_OF_2(size)) - printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size); - if (size < 4 * KiB) - printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size); - if (base % size != 0) - printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base, - size); - - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - void clear_all_var_mtrr(void) { - msr_t mtrr = { .raw = 0 }; int vcnt; - int i; vcnt = get_var_mtrr_count(); - for (i = 0; i < vcnt; i++) { - wrmsr(MTRR_PHYS_MASK(i), mtrr); - wrmsr(MTRR_PHYS_BASE(i), mtrr); - } + for (int i = 0; i < vcnt; i++) + clear_var_mtrr(i); } void var_mtrr_context_init(struct var_mtrr_context *ctx) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 0d31cab769e6..33fc46e362de 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -369,14 +369,6 @@ struct var_mtrr_state { struct var_mtrr_regs *regs; }; -static void clear_var_mtrr(int index) -{ - msr_t msr = { .lo = 0, .hi = 0 }; - - wrmsr(MTRR_PHYS_BASE(index), msr); - wrmsr(MTRR_PHYS_MASK(index), msr); -} - static int get_os_reserved_mtrrs(void) { return CONFIG(RESERVE_MTRRS_FOR_OS) ? 2 : 0; diff --git a/src/cpu/x86/mtrr/mtrrlib.c b/src/cpu/x86/mtrr/mtrrlib.c new file mode 100644 index 000000000000..fe6bd6aef51e --- /dev/null +++ b/src/cpu/x86/mtrr/mtrrlib.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <commonlib/bsd/helpers.h> +#include <types.h> + +/* + * Get first available variable MTRR. + * Returns var# if available, else returns -1. + */ +int get_free_var_mtrr(void) +{ + msr_t maskm; + int vcnt; + int i; + + vcnt = get_var_mtrr_count(); + + /* Identify the first var mtrr which is not valid. */ + for (i = 0; i < vcnt; i++) { + maskm = rdmsr(MTRR_PHYS_MASK(i)); + if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0) + return i; + } + + /* No free var mtrr. */ + return -1; +} + +/* + * Sets the specified variable MTRR (as per index) with the + * given base, size, and memory type. + */ +void set_var_mtrr( + unsigned int index, unsigned int base, unsigned int size, + unsigned int type) +{ + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + /* FIXME: It only support 4G less range */ + msr_t basem, maskm; + + if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM) + printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n", + type); + if (!IS_POWER_OF_2(size)) + printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size); + if (size < 4 * KiB) + printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size); + if (base % size != 0) + printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base, + size); + + basem.lo = base | type; + basem.hi = 0; + wrmsr(MTRR_PHYS_BASE(index), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; + maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + wrmsr(MTRR_PHYS_MASK(index), maskm); +} + +/* Disables the variable MTRR at the given index by clearing its base and mask MSRs. */ +void clear_var_mtrr(int index) +{ + msr_t msr = { .lo = 0, .hi = 0 }; + + wrmsr(MTRR_PHYS_BASE(index), msr); + wrmsr(MTRR_PHYS_MASK(index), msr); +} + +/* + * Acquires a free variable MTRR, configures it with the given base, size, and type. + * Returns the MTRR index if successful (>=0), or an error code (<0) if acquisition failed. + */ +int acquire_and_configure_mtrr(unsigned int base, unsigned int size, unsigned int type) +{ + int index = get_free_var_mtrr(); + + if (index >= 0) + set_var_mtrr(index, base, size, type); + + return index; +} diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index b7d700fb3946..6057282d765d 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/x86/cr.h> +#include <cpu/x86/gdt.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> -#include <arch/ram_segs.h> #define __RAMSTAGE__ #include <cpu/x86/64bit/entry64.inc> @@ -77,10 +77,10 @@ _start: orl $CR0_SET_FLAGS, %eax movl %eax, %cr0 - ljmpl $RAM_CODE_SEG, $1f + ljmpl $GDT_CODE_SEG, $1f 1: .code32 - movw $RAM_DATA_SEG, %ax + movw $GDT_DATA_SEG, %ax movw %ax, %ds movw %ax, %es movw %ax, %ss diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index d25b5f47cf4f..d9f64204d6da 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> +#include <arch/exception.h> #include <commonlib/region.h> #include <console/cbmem_console.h> #include <console/console.h> @@ -169,6 +170,9 @@ asmlinkage void smm_handler_start(void *arg) printk(BIOS_SPEW, "\nSMI# #%d\n", cpu); + if (CONFIG(DEBUG_SMI) && CONFIG(CONSOLE_SERIAL)) + exception_init(); + /* Allow drivers to initialize variables in SMM context. */ if (do_driver_init) { #if CONFIG(SPI_FLASH_SMM) diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index ae8e047f4efe..dcfbcba5909c 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -9,8 +9,8 @@ * found in smm.h. */ -#include <arch/rom_segs.h> #include <cpu/x86/cr.h> +#include <cpu/x86/gdt.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic_def.h> #include <cpu/x86/64bit/entry64.inc> @@ -48,7 +48,6 @@ fallback_stack_top: .code16 .global _start _start: -smm_handler_start: #if CONFIG(SMM_LAPIC_REMAP_MITIGATION) /* Check if the LAPIC register block overlaps with the stub. * This block needs to work without data accesses because they @@ -94,7 +93,7 @@ untampered_lapic: movl %eax, %cr0 /* Enable protected mode */ - ljmpl $ROM_CODE_SEG, $smm_trampoline32 + ljmpl $GDT_CODE_SEG, $smm_trampoline32 .align 4 smm_relocate_gdt: @@ -125,7 +124,7 @@ smm_relocate_gdt_end: .global smm_trampoline32 smm_trampoline32: /* Use flat data segment */ - movw $ROM_DATA_SEG, %ax + movw $GDT_DATA_SEG, %ax movw %ax, %ds movw %ax, %es movw %ax, %ss diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index ff33c0f4ba9d..39c504bad7d9 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -3,7 +3,7 @@ #define REALMODE_BASE 0x600 #define RELOCATED(x) (x - __realmode_code + REALMODE_BASE) -#include <arch/ram_segs.h> +#include <cpu/x86/gdt.h> /* CR0 bits */ #define PE (1 << 0) @@ -97,7 +97,7 @@ __realmode_call: movl %eax, __registers + 20 /* edi */ /* Activate the right segment descriptor real mode. */ - ljmp $RAM_CODE16_SEG, $RELOCATED(1f) + ljmp $GDT_CODE16_SEG, $RELOCATED(1f) 1: .code16 /* 16 bit code from here on... */ @@ -107,7 +107,7 @@ __realmode_call: * configurations (limits, writability, etc.) once * protected mode is turned off. */ - mov $RAM_DATA16_SEG, %ax + mov $GDT_DATA16_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -144,13 +144,13 @@ __realmode_call: movl __registers + 16, %esi movl __registers + 20, %edi - /* Set all segments to 0x0000, ds to 0x0040 */ + /* Set all segments to 0x0000, ds to 0x0038 */ push %ax xor %ax, %ax mov %ax, %es mov %ax, %fs mov %ax, %gs - mov $RAM_DATA_ACPI_SEG, %ax + mov $GDT_DATA_ACPI_SEG, %ax mov %ax, %ds pop %ax @@ -177,10 +177,10 @@ __lcall_instr = RELOCATED(.) /* Now that we are in protected mode * jump to a 32 bit code segment. */ - ljmpl $RAM_CODE_SEG, $RELOCATED(1f) + ljmpl $GDT_CODE_SEG, $RELOCATED(1f) 1: .code32 - mov $RAM_DATA_SEG, %ax + mov $GDT_DATA_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -233,7 +233,7 @@ __realmode_interrupt: movl %eax, __registers + 20 /* edi */ /* This configures CS properly for real mode. */ - ljmp $RAM_CODE16_SEG, $RELOCATED(1f) + ljmp $GDT_CODE16_SEG, $RELOCATED(1f) 1: .code16 /* 16 bit code from here on... */ @@ -241,7 +241,7 @@ __realmode_interrupt: * descriptors. They will retain these configurations (limits, * writability, etc.) once protected mode is turned off. */ - mov $RAM_DATA16_SEG, %ax + mov $GDT_DATA16_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -305,10 +305,10 @@ __intXX_instr = RELOCATED(.) movl %eax, %cr0 /* Now that we are in protected mode jump to a 32-bit code segment. */ - ljmpl $RAM_CODE_SEG, $RELOCATED(1f) + ljmpl $GDT_CODE_SEG, $RELOCATED(1f) 1: .code32 - mov $RAM_DATA_SEG, %ax + mov $GDT_DATA_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -354,10 +354,10 @@ __interrupt_handler_16bit = RELOCATED(.) movl %eax, %cr0 /* ... and jump to a 32 bit code segment. */ - ljmpl $RAM_CODE_SEG, $RELOCATED(1f) + ljmpl $GDT_CODE_SEG, $RELOCATED(1f) 1: .code32 - mov $RAM_DATA_SEG, %ax + mov $GDT_DATA_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -371,14 +371,14 @@ __interrupt_handler_16bit = RELOCATED(.) call *%eax /* Now return to real mode ... */ - ljmp $RAM_CODE16_SEG, $RELOCATED(1f) + ljmp $GDT_CODE16_SEG, $RELOCATED(1f) 1: .code16 /* Load the segment registers with properly configured segment * descriptors. They will retain these configurations (limits, * writability, etc.) once protected mode is turned off. */ - mov $RAM_DATA16_SEG, %ax + mov $GDT_DATA16_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 942591585d8e..715ec2a759bd 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -475,4 +475,22 @@ config BUILDING_WITH_DEBUG_FSP Enable this option if you are using a debug build of the FSP (Firmware Support Package) in your project. +config USE_COREBOOT_FOR_BMP_RENDERING + bool + default n + help + This option forces coreboot to use its native bitmap (BMP) image rendering + and skip using the FSP for this purpose during the boot process. + + If this option is selected (y), the platform will rely on the + coreboot native implementation for rendering BMP images. This might be + chosen if there are issues with FSP rendering or if native rendering + is preferred for specific reasons. + + If this option is not selected (n), the FSP's capabilities for BMP rendering + will be utilized. + + Platforms can choose to override this Kconfig option based on their + specific graphics requirements and FSP capabilities. + endif diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk index 18a62e3b5796..16905ca3734b 100644 --- a/src/drivers/intel/fsp2_0/Makefile.mk +++ b/src/drivers/intel/fsp2_0/Makefile.mk @@ -35,6 +35,7 @@ ramstage-$(CONFIG_FSP_NVS_DATA_POST_SILICON_INIT) += save_mrc_data.c ramstage-$(CONFIG_MMA) += mma_core.c ramstage-$(CONFIG_ENABLE_FSP_ERROR_INFO) += fsp_error_info_hob.c ramstage-$(CONFIG_BMP_LOGO) += fsp_gop_blt.c +ramstage-$(CONFIG_USE_COREBOOT_FOR_BMP_RENDERING) += cb_logo.c ifneq ($(CONFIG_NO_FSP_TEMP_RAM_EXIT),y) postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c diff --git a/src/drivers/intel/fsp2_0/cb_logo.c b/src/drivers/intel/fsp2_0/cb_logo.c new file mode 100644 index 000000000000..cc62a1c55339 --- /dev/null +++ b/src/drivers/intel/fsp2_0/cb_logo.c @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ + +#include <bootmode.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <device/pci_ops.h> +#include <fsp/api.h> +#include <fsp/fsp_gop_blt.h> +#include <fsp/graphics.h> +#include <fsp/util.h> +#include <intelblocks/graphics.h> +#include <soc/iomap.h> +#include <soc/soc_chip.h> +#include <stdlib.h> +#include <string.h> + +struct logo_coordinates { + uint32_t x; + uint32_t y; +}; + +/* + * Programs the Local Memory BAR (LMEMBAR) for the IGD. + * + * This function disables PCI command bits related to I/O, memory, and bus mastering + * for the IGD, programs the LMEMBAR with the provided base address, and then + * re-enables the PCI command bits. + */ +static void program_igd_lmembar(uint32_t base) +{ + const uint16_t disable_mask = ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + const uint16_t enable_mask = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Disable response in IO, MMIO space and Bus Master. */ + pci_and_config16(SA_DEV_IGD, PCI_COMMAND, disable_mask); + + /* Program IGD Base Address Register 2 aka LMEMBAR */ + pci_write_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_2, base); + + /* Enable response in IO, MMIO space and Bus Master. */ + pci_or_config16(SA_DEV_IGD, PCI_COMMAND, enable_mask); +} + +/* + * Calculates the destination coordinates for the logo based on alignment settings. + * + * horizontal_resolution: The horizontal resolution of the display panel. + * vertical_resolution: The vertical resolution of the display panel. + * logo_width: The width of the logo bitmap. + * logo_height: The height of the logo bitmap. + * valignment: The vertical alignment setting. + * + * Returning `struct logo_coordinates` that contains the calculated x and y coordinates + * for rendering the logo. + */ +static struct logo_coordinates calculate_logo_coordinates( + uint32_t horizontal_resolution, uint32_t vertical_resolution, + uint32_t logo_width, uint32_t logo_height, enum fw_splash_vertical_alignment valignment) +{ + struct logo_coordinates coords; + /* Always horizontally centered */ + coords.x = (horizontal_resolution - logo_width) / 2; + + switch (valignment) { + case FW_SPLASH_VALIGNMENT_MIDDLE: + coords.y = vertical_resolution / 2; + break; + case FW_SPLASH_VALIGNMENT_TOP: + coords.y = 0; + break; + case FW_SPLASH_VALIGNMENT_BOTTOM: + coords.y = vertical_resolution - logo_height; + break; + default: /* FW_SPLASH_VALIGNMENT_CENTER (default) */ + coords.y = (vertical_resolution - logo_height) / 2; + break; + } + + return coords; +} + +/* + * Copies the logo to the framebuffer. + * + * framebuffer_base: The base address of the framebuffer. + * bytes_per_scanline: The number of bytes per scanline in the framebuffer. + * logo_buffer_addr: The address of the logo data in BLT format. + * logo_width: The width of the logo bitmap. + * logo_height: The height of the logo bitmap. + * dest_x: The destination x-coordinate in the framebuffer for rendering the logo. + * dest_y: The destination y-coordinate in the framebuffer for rendering the logo. + */ +static void copy_logo_to_framebuffer( + uintptr_t framebuffer_base, uint32_t bytes_per_scanline, + efi_uintn_t logo_buffer_addr, uint32_t logo_width, uint32_t logo_height, + efi_uintn_t dest_x, efi_uintn_t dest_y) +{ + size_t pixel_size = sizeof(efi_graphics_output_blt_pixel); + size_t logo_line_bytes = logo_width * pixel_size; + efi_uintn_t framebuffer_offset = framebuffer_base + dest_y * bytes_per_scanline + + dest_x * pixel_size; + uint8_t *dst_row_address = (uint8_t *)framebuffer_offset; + uint8_t *src_row_address = (uint8_t *)(uintptr_t)logo_buffer_addr; + for (uint32_t i = 0; i < logo_height; i++) { + memcpy(dst_row_address, src_row_address, logo_line_bytes); + dst_row_address += bytes_per_scanline; + src_row_address += logo_line_bytes; + } +} + +void soc_load_logo_by_coreboot(void) +{ + size_t size; + const struct hob_graphics_info *ginfo; + struct soc_intel_common_config *config = chip_get_common_soc_structure(); + efi_uintn_t logo, blt_size; + efi_uintn_t blt_buffer_addr; + uint32_t logo_size, logo_height, logo_width; + int temp_mtrr_index = -1; + + /* Find the graphics information HOB */ + ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); + if (!ginfo || ginfo->framebuffer_base == 0) { + printk(BIOS_ERR, "Graphics information HOB not found or invalid framebuffer base.\n"); + return; + } + + /* Program the IGD LMEMBAR */ + program_igd_lmembar(GMADR_BASE); + + /* Set up a temporary Write Combine (WC) MTRR for the GMADR range */ + temp_mtrr_index = acquire_and_configure_mtrr(GMADR_BASE, GMADR_SIZE, MTRR_TYPE_WRCOMB); + if (temp_mtrr_index < 0) { + printk(BIOS_ERR, "Failed to configure WC MTRR for GMADR.\n"); + return; + } + + uintptr_t framebuffer_bar = ginfo->framebuffer_base; + uint32_t horizontal_resolution = ginfo->horizontal_resolution; + uint32_t vertical_resolution = ginfo->vertical_resolution; + uint32_t bytes_per_scanline = ginfo->pixels_per_scanline * + sizeof(efi_graphics_output_blt_pixel); + + /* + * Adjusts panel orientation for external display when the lid is closed. + * + * When the lid is closed, indicating the onboard display is inactive, + * below logic forces the panel orientation to normal. This ensures proper display + * on an external monitor, as rotated orientations are typically not suitable in + * such state. + */ + if (CONFIG(VBOOT_LID_SWITCH) ? !get_lid_switch() : !CONFIG(RUN_FSP_GOP)) + config->panel_orientation = LB_FB_ORIENTATION_NORMAL; + + /* Convert BMP logo to GOP BLT format */ + fsp_convert_bmp_to_gop_blt(&logo, &logo_size, &blt_buffer_addr, &blt_size, + &logo_height, &logo_width, config->panel_orientation); + + /* Override logo alignment if the default screen orientation is not normal */ + if (config->panel_orientation != LB_FB_ORIENTATION_NORMAL) + config->logo_valignment = FW_SPLASH_VALIGNMENT_CENTER; + + /* Calculate logo destination coordinates */ + struct logo_coordinates logo_coords = calculate_logo_coordinates(horizontal_resolution, + vertical_resolution, logo_width, logo_height, config->logo_valignment); + + /* Copy the logo to the framebuffer */ + copy_logo_to_framebuffer(framebuffer_bar, bytes_per_scanline, blt_buffer_addr, logo_width, + logo_height, logo_coords.x, logo_coords.y); + + /* Clear temporary Write Combine (WC) MTRR */ + clear_var_mtrr(temp_mtrr_index); +} diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index b7466a55ab5e..08609b67c183 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -15,25 +15,6 @@ enum pixel_format { pixel_bitmask = 2, /* defined by <rgb>_mask values */ }; -static const uint8_t fsp_graphics_info_guid[16] = { - 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, - 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 -}; - -struct hob_graphics_info { - uint64_t framebuffer_base; - uint32_t framebuffer_size; - uint32_t version; - uint32_t horizontal_resolution; - uint32_t vertical_resolution; - uint32_t pixel_format; /* See enum pixel_format */ - uint32_t red_mask; - uint32_t green_mask; - uint32_t blue_mask; - uint32_t reserved_mask; - uint32_t pixels_per_scanline; -} __packed; - struct pixel { uint8_t pos; uint8_t size; diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 0cbefbe9ae41..9ff32be6fcf3 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -85,8 +85,33 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase); /* Initialize memory margin analysis settings. */ void setup_mma(FSP_M_CONFIG *memory_cfg); -/* Update the SOC specific logo param and load the logo. */ -void soc_load_logo(FSPS_UPD *supd); +/* + * Populate UPD entries for the logo if the platform utilizes + * the FSP's capability for rendering bitmap (BMP) images. + */ +void soc_load_logo_by_fsp(FSPS_UPD *supd); +/* + * API that allows coreboot to perform native logo rendering after FSP display initialization. + * + * This implementation handles rendering the boot logo directly within coreboot. + * It depends on the FSP to initialize the display panel. + * Once the FSP completes display initialization and transfers control, coreboot + * renders the logo. + * + * Note: This native approach may introduce a ~10-30ms delay in displaying + * BMP images compared to rendering via FSP (when `USE_COREBOOT_FOR_BMP_RENDERING` + * Kconfig is not enable). + * + * coreboot native logo rendering provides greater flexibility for platform-specific + * logo customizations (e.g., alignment) that are not feasible or practical to implement + * within the FSP (silicon firmware) depending upon the OEM device need. + */ +#if CONFIG(USE_COREBOOT_FOR_BMP_RENDERING) +void soc_load_logo_by_coreboot(void); +#else +static inline void soc_load_logo_by_coreboot(void) { /* nop */ } +#endif + /* Update the SOC specific memory config param for mma. */ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); diff --git a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h index 4e1f68952e1b..377607929a83 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h +++ b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h @@ -3,6 +3,7 @@ #ifndef FSP_GOP_BLT_H #define FSP_GOP_BLT_H +#include <boot/coreboot_tables.h> #include <efi/efi_datatype.h> #include <types.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/graphics.h b/src/drivers/intel/fsp2_0/include/fsp/graphics.h index a5f781f87fc6..7348237f1b09 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/graphics.h +++ b/src/drivers/intel/fsp2_0/include/fsp/graphics.h @@ -5,6 +5,25 @@ #include <types.h> +static const uint8_t fsp_graphics_info_guid[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + +struct hob_graphics_info { + uint64_t framebuffer_base; + uint32_t framebuffer_size; + uint32_t version; + uint32_t horizontal_resolution; + uint32_t vertical_resolution; + uint32_t pixel_format; /* See enum pixel_format */ + uint32_t red_mask; + uint32_t green_mask; + uint32_t blue_mask; + uint32_t reserved_mask; + uint32_t pixels_per_scanline; +} __packed; + /* * Report the fsp_graphics_info_guid HOB to framebuffer info. * diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index f3472420bc6f..76636dd7a89e 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -124,9 +124,12 @@ static void do_silicon_init(struct fsp_header *hdr) /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); - /* Populate logo related entries */ - if (CONFIG(BMP_LOGO)) - soc_load_logo(upd); + /* + * Populate UPD entries for the logo if the platform utilizes + * the FSP's capability for rendering bitmap (BMP) images. + */ + if (CONFIG(BMP_LOGO) && !CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)) + soc_load_logo_by_fsp(upd); /* Call SiliconInit */ silicon_init = (void *)(uintptr_t)(hdr->image_base + @@ -154,6 +157,17 @@ static void do_silicon_init(struct fsp_header *hdr) fsp_debug_after_silicon_init(status); fsps_return_value_handler(FSP_SILICON_INIT_API, status); + /* + * Only applies for SoC platforms prior to FSP 2.2 specification: + * If a BMP logo is enabled (`BMP_LOGO`) and the platform is + * configured to skip the FSP for rendering logo bitmap + * (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot + * native function to handle BMP logo loading and display. + */ + if (!CONFIG(PLATFORM_USES_FSP2_2) && CONFIG(BMP_LOGO) && + CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)) + soc_load_logo_by_coreboot(); + /* Reinitialize CPUs if FSP-S has done MP Init */ if (CONFIG(USE_INTEL_FSP_MP_INIT) && !fsp_is_multi_phase_init_enabled()) do_mpinit_after_fsp(); @@ -202,6 +216,15 @@ static void do_silicon_init(struct fsp_header *hdr) timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END); post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT); + /* + * If a BMP logo is enabled (`BMP_LOGO`) and the platform is + * configured to skip the FSP for rendering logo bitmap + * (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot + * native function to handle BMP logo loading and display. + */ + if (CONFIG(BMP_LOGO) && CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)) + soc_load_logo_by_coreboot(); + /* Reinitialize CPUs if FSP-S has done MP Init */ if (CONFIG(USE_INTEL_FSP_MP_INIT)) do_mpinit_after_fsp(); @@ -269,7 +292,7 @@ void fsp_silicon_init(void) fsp_display_timestamp(); } -__weak void soc_load_logo(FSPS_UPD *supd) { } +__weak void soc_load_logo_by_fsp(FSPS_UPD *supd) { } static void release_logo(void *arg_unused) { diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c index 1cbf9fb28a5f..507678754c94 100644 --- a/src/drivers/smmstore/ramstage.c +++ b/src/drivers/smmstore/ramstage.c @@ -28,6 +28,10 @@ void lb_smmstorev2(struct lb_header *header) store->size = sizeof(*store); store->com_buffer = (uintptr_t)cbmem_entry_start(e); store->com_buffer_size = cbmem_entry_size(e); + if (info.mmap_addr < 4ULL * GiB) + store->mmap_addr_deprecated = info.mmap_addr; + else + store->mmap_addr_deprecated = 0; store->mmap_addr = info.mmap_addr; store->num_blocks = info.num_blocks; store->block_size = info.block_size; diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index 27a863ee3308..767e79467fee 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -3,16 +3,28 @@ #ifndef CPU_X86_GDT #define CPU_X86_GDT +#ifndef __ASSEMBLER__ /* These symbols are defined in c_start.S. */ extern char gdt[]; extern char per_cpu_segment_descriptors[]; extern uint32_t per_cpu_segment_selector; extern char gdt_end[]; extern char idtarg[]; +#endif -/* These symbols are defined in secondary.S. */ -extern char _secondary_gdt_addr[]; -extern char _secondary_start[]; -extern char _secondary_start_end[]; +/* Offset to GDT's segment descriptors: */ +#define GDT_CODE_SEG 0x08 +#define GDT_DATA_SEG 0x10 +#define GDT_CODE_SEG64 0x18 +/* + * This define is placed here to make sure future romstage programmers + * know about it. + * It is used only in SMM for STM setup code. + */ +#define GDT_TASK_STATE_SEG 0x20 + +#define GDT_CODE16_SEG 0x28 +#define GDT_DATA16_SEG 0x30 +#define GDT_DATA_ACPI_SEG 0x38 #endif /* CPU_X86_GDT */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 930edfdef7d6..87aee95c67f4 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -124,9 +124,11 @@ static inline int get_var_mtrr_count(void) return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT; } -void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, +int acquire_and_configure_mtrr(unsigned int base, unsigned int size, unsigned int type); +void set_var_mtrr(unsigned int index, unsigned int base, unsigned int size, unsigned int type); int get_free_var_mtrr(void); +void clear_var_mtrr(int index); void clear_all_var_mtrr(void); asmlinkage void display_mtrrs(void); diff --git a/src/include/smmstore.h b/src/include/smmstore.h index 595fe8b29bd5..4ee4c55c750b 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -69,7 +69,7 @@ struct smmstore_params_init { struct smmstore_params_info { uint32_t num_blocks; uint32_t block_size; - uint32_t mmap_addr; + uint64_t mmap_addr; } __packed; /* diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index 99169315456a..75b50a199db7 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -# TODO: Update for birman - chip soc/amd/phoenix register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 4c4fd7e2be8c..d09ed1e244ab 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -12,6 +12,16 @@ config BOARD_ASUS_H61_SERIES select SOUTHBRIDGE_INTEL_BD82X6X select USE_NATIVE_RAMINIT +config BOARD_ASUS_H61M_A_USB3 + select BOARD_ASUS_H61_SERIES + select BOARD_ROMSIZE_KB_8192 + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select NO_UART_ON_SUPERIO + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SUPERIO_NUVOTON_NCT6779D + config BOARD_ASUS_H61M_CS select BOARD_ASUS_H61_SERIES select BOARD_ROMSIZE_KB_8192 @@ -75,12 +85,13 @@ config MAINBOARD_DIR default "asus/h61-series" config VARIANT_DIR - default "h61m-cs" if BOARD_ASUS_H61M_CS - default "p8h61-m_lx" if BOARD_ASUS_P8H61_M_LX - default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0 - default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO + default "h61m-a_usb3" if BOARD_ASUS_H61M_A_USB3 + default "h61m-cs" if BOARD_ASUS_H61M_CS + default "p8h61-m_lx" if BOARD_ASUS_P8H61_M_LX + default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0 + default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO default "p8h61-m_pro_cm6630" if BOARD_ASUS_P8H61_M_PRO_CM6630 - default "p8h67-i_deluxe" if BOARD_ASUS_P8H67_I_DELUXE + default "p8h67-i_deluxe" if BOARD_ASUS_P8H67_I_DELUXE config MAINBOARD_PART_NUMBER default "H61M-CS" if BOARD_ASUS_H61M_CS diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name index eee48c0f91c7..e1e2317f093d 100644 --- a/src/mainboard/asus/h61-series/Kconfig.name +++ b/src/mainboard/asus/h61-series/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_ASUS_H61M_A_USB3 + bool "H61M-A/USB3" + config BOARD_ASUS_H61M_CS bool "H61M-CS" diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/board_info.txt b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/board_info.txt new file mode 100644 index 000000000000..9008bcc862cc --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/h61mausb3/helpdesk_knowledge/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.default b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.default new file mode 100644 index 000000000000..76c0b2d6ce33 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.default @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.layout b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.layout new file mode 100644 index 000000000000..227711afa286 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/cmos.layout @@ -0,0 +1,65 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/data.vbt b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/data.vbt Binary files differnew file mode 100644 index 000000000000..7739a7fb36d2 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/data.vbt diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/early_init.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/early_init.c new file mode 100644 index 000000000000..37da16c471b6 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/early_init.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states. */ + pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x24, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power RAM in S3. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); +} diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gma-mainboard.ads new file mode 100644 index 000000000000..20c53ef0f44b --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe. Thus, probe ports that likely have a high-resolution + -- display attached first. + + ports : constant Port_List := + (HDMI2, -- mainboard HDMI port + HDMI1, -- mainboard DVI-D port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gpio.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gpio.c new file mode 100644 index 000000000000..66fc05a68059 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/gpio.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio57 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c new file mode 100644 index 000000000000..1af52eb94e7e --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/hda_verb.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438445), + AZALIA_PIN_CFG(0, 0x11, 0x40330000), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a19040), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4024c601), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + + 0x8086281c, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h61-series/variants/h61m-a_usb3/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/overridetree.cb new file mode 100644 index 000000000000..be9667a328d9 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/h61m-a_usb3/overridetree.cb @@ -0,0 +1,82 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + device domain 0 on + subsystemid 0x1043 0x844d inherit + chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 0x95f, 0 }, + { 1, 0x95f, 0 }, + { 1, 0x9df, 1 }, + { 1, 0xfff, 1 }, + { 1, 0x95f, 2 }, + { 1, 0xfbf, 2 }, + { 1, 0xb57, 3 }, + { 1, 0xb57, 3 }, + { 1, 0x353, 4 }, + { 1, 0x353, 4 }, + { 1, 0xb5f, 6 }, + { 1, 0xb5f, 5 }, + { 1, 0xb57, 5 }, + { 1, 0xb57, 6 }, + }" + register "pcie_port_coalesce" = "1" + register "gen1_dec" = "0x000c0291" + device ref hda on + subsystemid 0x1043 0x8445 + end + device ref pcie_rp1 off end + device ref pcie_rp2 on end # ASM1042 USB 3.0 controller + device ref pcie_rp3 off end + device ref pcie_rp4 on end # PCIEX1_1 slot + device ref pcie_rp5 on end # PCIEX1_2 slot + device ref pcie_rp6 on # Realtek Gigabit NIC + device pci 00.0 on end + end + device ref pcie_rp7 off end + device ref pcie_rp8 off end + + device ref lpc on + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe7 = 0x11 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-pull/Open-drain selection + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c index d453adb1810b..667a369604e8 100644 --- a/src/mainboard/google/brya/variants/uldrenite/gpio.c +++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c @@ -143,18 +143,18 @@ static const struct pad_config gpio_table[] = { PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG), /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), - /* D13 : UART0_ISH_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), - /* D14 : UART0_ISH_TXD ==> LCD_CBL_DET# */ - PAD_CFG_GPO(GPP_D14, 1, DEEP), + /* D13 : UART0_ISH_RXD */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : UART0_ISH_TXD */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */ PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> SOC_TS_I2C_INT# */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), - /* D17 : NC ==> UART1_ISH_RX_DBG_TX */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), - /* D18 : NC ==> UART1_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2), + /* D17 : NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : LCD_CBL_DET# */ + PAD_CFG_GPO(GPP_D18, 1, DEEP), /* D19 : I2S_MCLK1_OUT ==> NC */ PAD_NC(GPP_D19, NONE), diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index 532752837f34..75809e233f94 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -8,6 +8,7 @@ #include <fw_config.h> #include <sar.h> #include <soc/bootblock.h> +#include <stdlib.h> const char *get_wifi_sar_cbfs_filename(void) { @@ -40,7 +41,7 @@ static const struct pad_config lte_disable_pads[] = { PAD_NC(GPP_H23, NONE), }; -static const struct pad_config ish_disable_pads[] = { +static const struct pad_config ish_uart0_disable_pads[] = { /* A16 : ISH_GP5 ==> NC */ PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG), /* B5 : GPP_B5 ==> NC */ @@ -49,12 +50,46 @@ static const struct pad_config ish_disable_pads[] = { PAD_NC(GPP_B6, NONE), /* D1 : ISH_GP1 ==> NC */ PAD_NC(GPP_D1, NONE), + /* D13 : UART0_ISH_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : UART0_ISH_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), + /* E9 : SOC_ACC2_INT ==> NC */ + PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), +}; + +static const struct pad_config switch_ish_uart1_pads[] = { + /* D13 : UART0_ISH_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : UART0_ISH_TXD ==> LCD_CBL_DET# */ + PAD_CFG_GPO(GPP_D14, 1, DEEP), + /* D17 : NC ==> UART1_ISH_RDX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + /* D18 : LCD_CBL_DET# ==> UART1_ISH_TDX */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2), +}; + +static const struct pad_config ish_uart1_disable_pads[] = { + /* A16 : ISH_GP5 ==> NC */ + PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG), + /* B5 : GPP_B5 ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : GPP_B6 ==> NC */ + PAD_NC(GPP_B6, NONE), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D17 : UART1_ISH_RDX ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : UART1_ISH_TDX ==> NC*/ + PAD_NC(GPP_D18, NONE), /* E9 : SOC_ACC2_INT ==> NC */ PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), }; void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { + uint32_t board_version = board_id(); + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) { printk(BIOS_INFO, "Disable touchscreen GPIO pins.\n"); gpio_padbased_override(padbased_table, touchscreen_disable_pads, @@ -65,10 +100,24 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); } - if (!fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) { - printk(BIOS_INFO, "Disable ISH GPIO pins.\n"); - gpio_padbased_override(padbased_table, ish_disable_pads, - ARRAY_SIZE(ish_disable_pads)); + + /* b/415605630: Support different ISH UART mappings according the board id */ + if (board_version < 2) { + /* Override ISH UART0 to ISH UART1 */ + gpio_padbased_override(padbased_table, switch_ish_uart1_pads, + ARRAY_SIZE(switch_ish_uart1_pads)); + + if (!fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) { + printk(BIOS_INFO, "Disable ISH GPIO pins is based on ISH UART1.\n"); + gpio_padbased_override(padbased_table, ish_uart1_disable_pads, + ARRAY_SIZE(ish_uart1_disable_pads)); + } + } else { + if (!fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) { + printk(BIOS_INFO, "Disable ISH GPIO pins is based on ISH UART0.\n"); + gpio_padbased_override(padbased_table, ish_uart0_disable_pads, + ARRAY_SIZE(ish_uart0_disable_pads)); + } } } @@ -122,3 +171,17 @@ void variant_update_descriptor(void) configure_descriptor(fivr_bytes, ARRAY_SIZE(fivr_bytes)); } } + +void variant_configure_pads(void) +{ + const struct pad_config *base_pads; + struct pad_config *padbased_table; + size_t base_num; + + padbased_table = new_padbased_table(); + base_pads = variant_gpio_table(&base_num); + gpio_padbased_override(padbased_table, base_pads, base_num); + fw_config_gpio_padbased_override(padbased_table); + gpio_configure_pads_with_padbased(padbased_table); + free(padbased_table); +} diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 484fd027cadf..cd14d2c10e54 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -22,6 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION select MAINBOARD_USES_IFD_EC_REGION select SMBIOS_SERIAL_FROM_VPD if VPD select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 565aad6f98a5..858205902d6a 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -128,6 +128,7 @@ chip soc/intel/pantherlake #| I2C5 | Touchpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ + .logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE, .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[1] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 82a632692abe..850234153f98 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -26,6 +26,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL select SPI_TPM select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb index 30daba557269..f0c1039c016d 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb @@ -288,7 +288,6 @@ chip soc/intel/pantherlake end end - device ref ipu off end device ref iaa off end device ref thc0 on @@ -356,8 +355,6 @@ chip soc/intel/pantherlake device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end - device ref tbt_pcie_rp2 on end - device ref tbt_pcie_rp3 on end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on @@ -373,18 +370,6 @@ chip soc/intel/pantherlake register "group" = "ACPI_PLD_GROUP(3, 2)" device ref tcss_usb3_port1 on end end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device ref tcss_usb3_port2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C3"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device ref tcss_usb3_port3 on end - end end end end @@ -401,18 +386,6 @@ chip soc/intel/pantherlake device generic 0 on end end end - device ref tcss_dma1 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port2 as dfp[0].typec_port - device generic 0 on end - end - chip drivers/intel/usb4/retimer - register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port3 as dfp[1].typec_port - device generic 0 on end - end - end device ref ish on probe ISH ISH_ENABLE @@ -578,22 +551,6 @@ chip soc/intel/pantherlake device generic 0 on end end end # Gen4 M.2 SSD - device ref pcie_rp9 on - probe STORAGE STORAGE_NVME_GEN5 - probe STORAGE STORAGE_UNKNOWN - register "pcie_rp[PCIE_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, - .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, - }" - chip soc/intel/common/block/pcie/rtd3 - register "is_storage" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" - register "srcclk_pin" = "1" - device generic 0 on end - end - end # Gen5 M.2 SSD device ref cnvi_wifi on probe WIFI WIFI_CNVI_6 probe WIFI WIFI_CNVI_7 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 5f678aa4befc..666fb8f7f070 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -20,6 +20,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_EC_REGION select SMBIOS_SERIAL_FROM_VPD if VPD + select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SOC_INTEL_WHISKEYLAKE diff --git a/src/mainboard/google/volteer/variants/elemi/ramstage.c b/src/mainboard/google/volteer/variants/elemi/ramstage.c index f7a174d88865..16261b7d45d7 100644 --- a/src/mainboard/google/volteer/variants/elemi/ramstage.c +++ b/src/mainboard/google/volteer/variants/elemi/ramstage.c @@ -3,17 +3,31 @@ #include <delay.h> #include <gpio.h> #include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> void variant_ramstage_init(void) { - /* - * Assert FPMCU reset and enable power to FPMCU, - * wait for power rail to stabilize, - * and then deassert FPMCU reset. - * Waiting for the power rail to stabilize can take a while. - */ - gpio_output(GPP_C23, 0); - gpio_output(GPP_A21, 1); - mdelay(1); - gpio_output(GPP_C23, 1); + uint32_t sku_id = google_chromeec_get_board_sku(); + + switch (sku_id) { + case 102: + case 104: + case 107: + case 109: + case 115: + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); + break; + default: + /* SKU does not have FP Sensor, do not enable FPMCU */ + break; + } } diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 16c68cd1a3c0..476e4f78dba1 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -43,33 +43,18 @@ chip soc/intel/cannonlake register "s0ix_enable" = "false" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.5 on end # SDCard - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 1e.0 on end # UART #0 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref xhci on end + device ref sdxc on end + device ref uart0 on end + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI + end + device ref hda on end + device ref smbus on end end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index a10d271610d5..d36f9e22a412 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -61,15 +61,11 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[9]" = "9" device domain 0 on - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 (Not available on PCH-H) - device pci 19.1 off end # I2C #5 (Not available on PCH-H) - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + device ref i2c0 on end + device ref i2c1 on end + device ref sata on end + device ref uart2 on end + device ref emmc on end device ref pcie_rp1 on # x4 SLOT1 register "PcieRpSlotImplemented[0]" = "1" end @@ -79,9 +75,6 @@ chip soc/intel/cannonlake device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" end - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.6 on end # GbE + device ref gbe on end end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index c8c443486fc7..607eb6a37155 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -63,21 +63,19 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[10]" = "10" device domain 0 on - device pci 14.3 on + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 (Not available on PCH-H) - device pci 19.1 off end # I2C #5 (Not available on PCH-H) - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref sata on end + device ref uart2 on end + device ref emmc on end device ref pcie_rp1 on register "PcieRpSlotImplemented[0]" = "1" end @@ -102,7 +100,6 @@ chip soc/intel/cannonlake device ref pcie_rp21 on # x4 SLOT 2 register "PcieRpSlotImplemented[20]" = "1" end - device pci 1e.1 off end # UART #1 - device pci 1f.6 on end # GbE + device ref gbe on end end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index 25d084ac163b..908632093c3e 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -38,16 +38,15 @@ chip soc/intel/cannonlake }" device domain 0 on - device pci 14.3 on + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on + end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c3 on chip drivers/i2c/max98373 register "interleave_mode" = "1" register "vmon_slot_no" = "4" @@ -57,12 +56,10 @@ chip soc/intel/cannonlake register "name" = ""MAXR"" device i2c 32 on end end - end # I2C #3 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + end + device ref i2c4 on end + device ref uart2 on end + device ref emmc on end device ref pcie_rp1 on # x4 SLOT1 register "PcieRpSlotImplemented[0]" = "1" end @@ -72,9 +69,5 @@ chip soc/intel/cannonlake device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" end - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.6 off end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 1f3bf9074bce..a14e9910c1ff 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -59,22 +59,19 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - device pci 14.3 on + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + end + device ref sdxc on end + device ref i2c0 on end + device ref i2c1 on end + device ref sata on end + device ref i2c4 on end + device ref uart2 on end + device ref emmc on end device ref pcie_rp1 on # x4 SLOT1 register "PcieRpSlotImplemented[0]" = "1" end @@ -84,7 +81,6 @@ chip soc/intel/cannonlake device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" end - device pci 1e.1 off end # UART #1 - device pci 1f.6 on end # GbE + device ref gbe on end end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 309082ed4d3b..ded8e72c2391 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -44,21 +44,18 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - device pci 14.3 on + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + end + device ref i2c0 on end + device ref i2c1 on end + device ref sata on end + device ref i2c4 on end + device ref uart2 on end + device ref emmc on end device ref pcie_rp1 on # x4 SLOT1 register "PcieRpSlotImplemented[0]" = "1" end @@ -68,7 +65,6 @@ chip soc/intel/cannonlake device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" end - device pci 1e.1 off end # UART #1 - device pci 1f.6 on end # GbE + device ref gbe on end end end diff --git a/src/mainboard/intel/ptlrvp/mainboard.c b/src/mainboard/intel/ptlrvp/mainboard.c index e14c5ace797c..5b80d9d650af 100644 --- a/src/mainboard/intel/ptlrvp/mainboard.c +++ b/src/mainboard/intel/ptlrvp/mainboard.c @@ -28,12 +28,15 @@ void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config * static void mainboard_init(void *chip_info) { struct pad_config *padbased_table; - const struct pad_config *base_pads; - size_t base_num; + const struct pad_config *base_pads, *variant_diff_pads; + size_t base_num, variant_diff_num; padbased_table = new_padbased_table(); base_pads = variant_gpio_table(&base_num); gpio_padbased_override(padbased_table, base_pads, base_num); + variant_diff_pads = variant_board_gpio_diff_table(&variant_diff_num); + if (variant_diff_pads) + gpio_padbased_override(padbased_table, variant_diff_pads, variant_diff_num); fw_config_gpio_padbased_override(padbased_table); gpio_configure_pads_with_padbased(padbased_table); free(padbased_table); diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h index 0ee09a5835ba..05ddf5bb5f27 100644 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h @@ -23,6 +23,7 @@ enum ptl_boardid { */ const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_board_gpio_diff_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_romstage_gpio_table(size_t *num); void fw_config_configure_pre_mem_gpio(void); diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk index b9f1fd15dd42..598167cbe49d 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk @@ -7,3 +7,4 @@ romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c index 9531065689c7..7b4dbe3c9f6b 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c @@ -3,10 +3,11 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> +#include <ec/intel/board_id.h> #include <soc/gpio.h> /* Pad configuration in ramstage*/ -static const struct pad_config gpio_table[] = { +static const struct pad_config t3_gpio_table[] = { /* GPP_A00: ESPI_IO0_EC_R */ /* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */ @@ -391,10 +392,48 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), }; +/* Pad difference in ramstage for LP5 T4 RVP */ +static const struct pad_config t4_gpio_diff_table[] = { + /* GPP_B09: MOD_TCSS2_DISP_HPD1 */ + PAD_CFG_NF(GPP_B09, NONE, DEEP, NF2), + /* GPP_B10: MOD_TCSS1_DISP_HPD2 */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2), + /* GPP_B11: GEN4_SSD_PWREN */ + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + + /* GPP_B14: Not used */ + PAD_NC(GPP_B14, NONE), + + /* GPP_B17: MOD_TCSS2_LSX_DIR_SEL_EDP_VDD_EN */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + /* GPP_C06: X4_PCIE_SLOT_PWR_EN_N */ + PAD_CFG_GPO(GPP_C06, 0, DEEP), + /* GPP_C07: X4_DT_PCIE_RST_N */ + PAD_CFG_GPO(GPP_C07, 1, DEEP), + + /* GPP_D01: MOD_TCSS2_TYP_A_VBUS_EN_EDP_BKLT_EN */ + PAD_CFG_NF(GPP_D01, NONE, DEEP, NF2), + /* GPP_D02: MOD_TCSS2_EDP_BKLT_CTRL */ + PAD_CFG_NF(GPP_D02, NONE, DEEP, NF2), + + /* GPP_D20: CLKREQ7_X4_GEN5_DT_CEM_SLOT_N */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* GPP_E08: M2_GEN4_SSD_RESET_N */ + PAD_CFG_GPO(GPP_E08, 1, PLTRST), + + /* GPP_F23: SMC_LID */ + PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, LEVEL, ACPI), + + /* GPP_V17: TCP_RT_S0IX_ENTRY_EXIT_N */ + PAD_CFG_GPO(GPP_V17, 1, PLTRST), +}; + const struct pad_config *variant_gpio_table(size_t *num) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + *num = ARRAY_SIZE(t3_gpio_table); + return t3_gpio_table; } const struct pad_config *variant_early_gpio_table(size_t *num) @@ -410,6 +449,24 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num) return romstage_gpio_table; } +const struct pad_config *variant_board_gpio_diff_table(size_t *num) +{ + int board_id = get_rvp_board_id(); + + switch (board_id) { + case PTLP_LP5_T3_RVP: + return NULL; + case PTLP_LP5_T4_RVP: + *num = ARRAY_SIZE(t4_gpio_diff_table); + return t4_gpio_diff_table; + case GCS_32GB: + case GCS_64GB: + return NULL; + default: + die("Unknown board ID = 0x%x\n", board_id); + } +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME), CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME), diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c index 6a1706fe9fe1..350405dc2920 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c @@ -65,7 +65,7 @@ static const struct mb_cfg gcs_mem_config = { }, }; -static const struct mb_cfg lp5_mem_config = { +static const struct mb_cfg lp5_t3_mem_config = { .type = MEM_TYPE_LP5X, .lpx_dq_map = { @@ -125,6 +125,66 @@ static const struct mb_cfg lp5_mem_config = { }, }; +static const struct mb_cfg lp5_t4_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 10, 8, 11, 9, 15, 12, 14, 13 }, + .dq1 = { 6, 7, 5, 4, 3, 1, 0, 2 }, + }, + .ddr1 = { + .dq0 = { 1, 0, 3, 2, 7, 6, 5, 4 }, + .dq1 = { 14, 13, 12, 15, 11, 9, 8, 10 }, + }, + .ddr2 = { + .dq0 = { 13, 14, 12, 15, 8, 10, 9, 11 }, + .dq1 = { 6, 7, 5, 4, 1, 3, 2, 0 }, + }, + .ddr3 = { + .dq0 = { 6, 5, 7, 4, 3, 2, 0, 1 }, + .dq1 = { 14, 13, 12, 15, 11, 9, 8, 10 }, + }, + .ddr4 = { + .dq0 = { 10, 8, 9, 11, 13, 12, 14, 15 }, + .dq1 = { 1, 3, 0, 2, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 1, 0, 2, 3, 7, 6, 5, 4 }, + .dq1 = { 10, 8, 11, 9, 13, 12, 14, 15 }, + }, + .ddr6 = { + .dq0 = { 10, 8, 11, 9, 13, 12, 14, 15 }, + .dq1 = { 6, 5, 7, 4, 0, 1, 2, 3 }, + }, + .ddr7 = { + .dq0 = { 1, 0, 2, 3, 7, 4, 6, 5 }, + .dq1 = { 14, 13, 15, 12, 10, 11, 9, 8 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .lp_ddr_dq_dqs_re_training = 1, + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + static const struct mb_cfg ddr5_mem_config = { .type = MEM_TYPE_DDR5, @@ -149,8 +209,9 @@ const struct mb_cfg *variant_memory_params(void) switch (board_id) { case PTLP_LP5_T3_RVP: + return &lp5_t3_mem_config; case PTLP_LP5_T4_RVP: - return &lp5_mem_config; + return &lp5_t4_mem_config; case GCS_32GB: case GCS_64GB: return &gcs_mem_config; diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk index 1a93597f4e47..5575815d1b21 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk @@ -6,3 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068 SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 1(0b0001) Parts = H58G66BK8BX067 +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = H58G56BK8BX068 diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt index 7f7236d0eca2..244c063804ef 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt @@ -6,3 +6,4 @@ DRAM Part Name ID to assign H58G56BK7BX068 0 (0000) H58G66BK8BX067 1 (0001) +H58G56BK8BX068 2 (0010) diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt index 86a6e201d78f..98255ad4d3b3 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt @@ -11,3 +11,4 @@ # Part Name H58G56BK7BX068 H58G66BK8BX067 +H58G56BK8BX068 diff --git a/src/mainboard/lenovo/m900_tiny/data.vbt b/src/mainboard/lenovo/m900_tiny/data.vbt Binary files differindex 7e6fe3dc1399..4c26ae512bd8 100644 --- a/src/mainboard/lenovo/m900_tiny/data.vbt +++ b/src/mainboard/lenovo/m900_tiny/data.vbt diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index 0aa6cbe7b4d6..82d1a21a0e94 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -97,15 +97,17 @@ const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_B23, 0, DEEP), /* XTAL [ 38.4Mhz / 19.2MHz ] */ - PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_B22, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* BFX Strap 2 Bit 1 [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_H0, 0, RSMRST), /* BFX Strap 2 Bit 2 [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_H2, 0, RSMRST), /* BFX Strap 2 Bit 4 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1,8V / 3.3V ] */ PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */ PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), /* CPUNSSC [ 19.2MHz / 38.4MHz ] */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), /* XTAL Mode [ Attached / Single ] */ PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE), @@ -140,8 +142,6 @@ const struct pad_config gpio_table[] = { PAD_NC(GPP_B19, NONE), PAD_NC(GPP_B20, NONE), PAD_NC(GPP_B21, NONE), - PAD_NC(GPP_B22, NONE), - PAD_NC(GPP_C3, NONE), PAD_NC(GPP_C4, NONE), PAD_NC(GPP_C9, NONE), @@ -198,7 +198,6 @@ const struct pad_config gpio_table[] = { PAD_NC(GPP_F6, NONE), PAD_NC(GPP_F8, NONE), PAD_NC(GPP_F9, NONE), - PAD_NC(GPP_F10, NONE), PAD_NC(GPP_F11, NONE), PAD_NC(GPP_F12, NONE), PAD_NC(GPP_F13, NONE), @@ -213,6 +212,7 @@ const struct pad_config gpio_table[] = { PAD_NC(GPP_F22, NONE), PAD_NC(GPP_F23, NONE), + /* H3: Not Connected */ PAD_NC(GPP_H3, NONE), PAD_NC(GPP_H4, NONE), PAD_NC(GPP_H5, NONE), diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 9c5ae5264e5b..99e62c77c032 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -4,6 +4,7 @@ #include <security/intel/stm/SmmStm.h> #include <security/intel/stm/StmPlatformResource.h> #include <security/tpm/tspi.h> +#include <cpu/x86/gdt.h> #include <cpu/x86/smm.h> #include <cpu/x86/msr.h> @@ -11,7 +12,6 @@ #include <console/console.h> #include <stdbool.h> #include <stdint.h> -#include <arch/rom_segs.h> /* * Load STM image to MSEG @@ -109,11 +109,11 @@ void setup_smm_descriptor(void *smbase, int32_t apic_id, int32_t entry32_off) psd->acpi_rsdp = 0; psd->bios_hw_resource_requirements_ptr = (uint64_t)((uintptr_t)get_stm_resource()); - psd->smm_cs = ROM_CODE_SEG; - psd->smm_ds = ROM_DATA_SEG; - psd->smm_ss = ROM_DATA_SEG; - psd->smm_other_segment = ROM_DATA_SEG; - psd->smm_tr = SMM_TASK_STATE_SEG; + psd->smm_cs = GDT_CODE_SEG; + psd->smm_ds = GDT_DATA_SEG; + psd->smm_ss = GDT_DATA_SEG; + psd->smm_other_segment = GDT_DATA_SEG; + psd->smm_tr = GDT_TASK_STATE_SEG; // At this point the coreboot smm_stub is relative to the default // smbase and not the one for the smi handler in tseg. So we have diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index ff9db05f0608..9c0f5319a3f7 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -3,7 +3,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> -#include <arch/ram_segs.h> +#include <cpu/x86/gdt.h> #include "getsec_mtrr_setup.inc" @@ -257,10 +257,10 @@ cond_clear_var_mtrrs: lgdt -48(%ebp) /* Set cs */ - ljmp $RAM_CODE_SEG, $1f + ljmp $GDT_CODE_SEG, $1f 1: /* Fix segment registers */ - movl $RAM_DATA_SEG, %eax + movl $GDT_DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index 5393eba911f7..23b2cfe5ced3 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -59,7 +59,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) payload_preload(); } -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { size_t logo_size; supd->FspsConfig.logo_bmp_buffer = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 995b1cc535f7..ac227b9f6fd0 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only # TODO: Evaluate what can be moved to a common directory -# TODO: Update for Phoenix config SOC_AMD_PHOENIX_BASE bool diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index 878ebe7bb7c6..68cc935f7535 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -1,7 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # TODO: Move as much as possible to common -# TODO: Update for Phoenix ifeq ($(CONFIG_SOC_AMD_PHOENIX_BASE),y) diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 1475b6166ad9..0f0ec26daebc 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ /* TODO: See what can be made common */ /* ACPI - create the Fixed ACPI Description Tables (FADT) */ diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index eabd44518e1c..fb0ef0f78a22 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #ifndef PHOENIX_CHIP_H #define PHOENIX_CHIP_H diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk index 55fc83ea7c52..6262cf29993e 100644 --- a/src/soc/intel/alderlake/Makefile.mk +++ b/src/soc/intel/alderlake/Makefile.mk @@ -70,11 +70,6 @@ endif CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include -# Include the missing MemInfoHob.h from vendorcode -ifeq ($(CONFIG_SOC_INTEL_RAPTORLAKE_PCH_S)$(CONFIG_FSP_TYPE_IOT),yy) -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s -endif - ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) # 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples # 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 380f40ba601d..a788319efc6f 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1249,6 +1249,9 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, /* Override settings per board if required. */ mainboard_update_soc_chip_config(config); + /* Runtime configuration of S0ix */ + config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable); + void (*const fill_fsps_params[])(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) = { fill_fsps_lpss_params, @@ -1378,7 +1381,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { struct soc_intel_common_config *config = chip_get_common_soc_structure(); FSP_S_CONFIG *s_cfg = &supd->FspsConfig; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ab5b5d884d0f..c5553780ea59 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -914,7 +914,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { size_t logo_size; supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 993efbb10785..2e00018f369d 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -801,7 +801,7 @@ __weak void mainboard_silicon_init_params(FSPS_UPD *supd) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { size_t logo_size; supd->FspsConfig.LogoPtr = (uintptr_t)bmp_load_logo(&logo_size); diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index 856352096147..299e923d85c4 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -14,6 +14,76 @@ enum { }; /* + * Specifies the vertical alignment for the splash screen image. + * + * Visual Guide (representing the display area and the [LOGO]): + * + * Each option dictates the vertical placement of the splash image + * within the display's height. + */ +enum fw_splash_vertical_alignment { + /* FW_SPLASH_VALIGNMENT_CENTER: + * The splash image is centered vertically `(Y-axis - logo_height)/2` on the screen. + * The center of the [LOGO] aligns with the vertical center of the screen. + * + * +---------------+ + * | | + * | | + * | [LOGO] | <-- Vertically Centered + * | | + * | | + * +---------------+ + */ + FW_SPLASH_VALIGNMENT_CENTER = 0, + + /* FW_SPLASH_VALIGNMENT_TOP: + * The splash image is aligned to the top edge of the screen. + * + * +---------------+ + * | [LOGO] | <-- Top Aligned + * | | + * | | + * | | + * | | + * +---------------+ + */ + FW_SPLASH_VALIGNMENT_TOP = 1, + + /* FW_SPLASH_VALIGNMENT_BOTTOM: + * The splash image is aligned to the bottom edge of the screen. + * + * +---------------+ + * | | + * | | + * | | + * | | + * | [LOGO] | <-- Bottom Aligned + * +---------------+ + */ + FW_SPLASH_VALIGNMENT_BOTTOM = 2, + + /* FW_SPLASH_VALIGNMENT_MIDDLE: + * The splash image is placed in the vertical middle `(Y-axis/2)` of the screen + * (without considering the `logo height`). This means the TOP EDGE of the + * [LOGO] aligns with the screen's vertical midpoint line. + * + * +---------------+ + * | (Upper Half) | + * | | + * | [LOGO] | <-- [LOGO] aligns at Middle of the Y-axis + * | | + * | (Lower Half) | + * +---------------+ + * + * Note: The distinction between CENTER and MIDDLE is relevant as in for MIDDLE + * alignment, it ignores the logo height (i.e., the logo's top edge is placed + * at the screen's Y-midpoint). CENTER alignment, by contrast, would place + * the geometrical center of the logo at the screen's Y-midpoint. + */ + FW_SPLASH_VALIGNMENT_MIDDLE = 3, +}; + +/* * This structure will hold data required by common blocks. * These are soc specific configurations which will be filled by soc. * We'll fill this structure once during init and use the data in common block. @@ -26,6 +96,7 @@ struct soc_intel_common_config { uint8_t pch_thermal_trip; struct mmc_dll_params emmc_dll; enum lb_fb_orientation panel_orientation; + enum fw_splash_vertical_alignment logo_valignment; }; /* This function to retrieve soc config structure required by common code */ diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 2f2e7408c470..082acaf7ae2c 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -505,6 +505,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); + + /* Runtime configuration of S0ix */ + config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable); } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 3bad53342407..b01610d2fed8 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -253,6 +253,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); + + /* Runtime configuration of S0ix */ + config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable); } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index ad85702dbeb7..30ea478432ba 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -784,6 +784,9 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, /* Override settings per board if required. */ mainboard_update_soc_chip_config(config); + /* Runtime configuration of S0ix */ + config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable); + void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) = { fill_fsps_lpss_params, @@ -868,7 +871,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { struct soc_intel_common_config *config = chip_get_common_soc_structure(); FSP_S_CONFIG *s_cfg = &supd->FspsConfig; diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 23eaaa61edf4..6787642f24e4 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -72,7 +72,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_IOC select SOC_INTEL_COMMON_BLOCK_IOE_P2SB - select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IPU if SOC_INTEL_PANTHERLAKE select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_ME_SPEC_21 select SOC_INTEL_COMMON_BLOCK_MEMINIT @@ -104,6 +104,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202302_BINDING + select USE_COREBOOT_FOR_BMP_RENDERING select USE_X86_64_SUPPORT select X86_INIT_NEED_1_SIPI help @@ -192,7 +193,8 @@ config HEAP_SIZE config CHIPSET_DEVICETREE string - default "soc/intel/pantherlake/chipset.cb" + default "soc/intel/pantherlake/chipset_wcl.cb" if SOC_INTEL_WILDCATLAKE + default "soc/intel/pantherlake/chipset_ptl.cb" config EXT_BIOS_WIN_BASE default 0xf8000000 @@ -230,15 +232,18 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config MAX_TBT_ROOT_PORTS int + default 2 if SOC_INTEL_WILDCATLAKE default 4 config MAX_ROOT_PORTS int + default 6 if SOC_INTEL_WILDCATLAKE default 10 if SOC_INTEL_PANTHERLAKE_H default 12 config MAX_PCIE_CLOCK_SRC int + default 6 if SOC_INTEL_WILDCATLAKE default 9 config SMM_TSEG_SIZE diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index 1c965f411ee1..0252e1c5032a 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -214,12 +214,14 @@ static struct min_sleep_state min_pci_sleep_states[] = { { PCI_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, +#if CONFIG(SOC_INTEL_PANTHERLAKE) { PCI_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, +#endif { PCI_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, { PCI_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, { PCI_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c index 28ec7473af32..07e12619161d 100644 --- a/src/soc/intel/pantherlake/bootblock/report_platform.c +++ b/src/soc/intel/pantherlake/bootblock/report_platform.c @@ -32,6 +32,8 @@ static struct { { PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" }, { PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" }, { PCI_DID_INTEL_PTL_H_ID_4, "Pantherlake H" }, + { PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" }, + { PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" }, }; static struct { @@ -102,6 +104,38 @@ static struct { { PCI_DID_INTEL_PTL_H_ESPI_29, "Pantherlake SOC-H" }, { PCI_DID_INTEL_PTL_H_ESPI_30, "Pantherlake SOC-H" }, { PCI_DID_INTEL_PTL_H_ESPI_31, "Pantherlake SOC-H" }, + { PCI_DID_INTEL_WCL_ESPI_0, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_1, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_2, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_3, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_4, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_5, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_6, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_7, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_8, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_9, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_10, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_11, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_12, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_13, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_14, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_15, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_16, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_17, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_18, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_19, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_20, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_21, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_22, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_23, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_24, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_25, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_26, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_27, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_28, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_29, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_30, "Wildcatlake SOC" }, + { PCI_DID_INTEL_WCL_ESPI_31, "Wildcatlake SOC" }, }; static struct { @@ -112,6 +146,8 @@ static struct { { PCI_DID_INTEL_PTL_H_GT2_1, "Pantherlake-H GT2" }, { PCI_DID_INTEL_PTL_H_GT2_2, "Pantherlake-H GT2" }, { PCI_DID_INTEL_PTL_H_GT2_3, "Pantherlake-H GT2" }, + { PCI_DID_INTEL_WCL_GT2_1, "Wildcatlake GT2" }, + { PCI_DID_INTEL_WCL_GT2_2, "Wildcatlake GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 5fe2a37043b8..317fa5fa0e13 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -102,12 +102,14 @@ const char *soc_acpi_name(const struct device *dev) case PCI_DEVFN_PCIE4: return "RP04"; case PCI_DEVFN_PCIE5: return "RP05"; case PCI_DEVFN_PCIE6: return "RP06"; +#if CONFIG(SOC_INTEL_PANTHERLAKE) case PCI_DEVFN_PCIE7: return "RP07"; case PCI_DEVFN_PCIE8: return "RP08"; case PCI_DEVFN_PCIE9: return "RP09"; case PCI_DEVFN_PCIE10: return "RP10"; case PCI_DEVFN_PCIE11: return "RP11"; case PCI_DEVFN_PCIE12: return "RP12"; +#endif case PCI_DEVFN_PMC: return "PMC"; case PCI_DEVFN_UART0: return "UAR0"; case PCI_DEVFN_UART1: return "UAR1"; diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset_ptl.cb index 0c57a7def608..0c57a7def608 100644 --- a/src/soc/intel/pantherlake/chipset.cb +++ b/src/soc/intel/pantherlake/chipset_ptl.cb diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb new file mode 100644 index 000000000000..c5f1d2bd1109 --- /dev/null +++ b/src/soc/intel/pantherlake/chipset_wcl.cb @@ -0,0 +1,132 @@ +chip soc/intel/pantherlake + + device cpu_cluster 0 on end + + # TODO: Add WCL power limits + + # Reduce the size of BasicMemoryTests to speed up the boot time. + register "lower_basic_mem_test_size" = "true" + + # NOTE: if any variant wants to override this value, use the same format + # as register "common_soc_config.pch_thermal_trip" = "value", instead of + # putting it under register "common_soc_config" in overridetree.cb file. + register "common_soc_config.pch_thermal_trip" = "125" + + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 02.0 alias igpu on end + device pci 04.0 alias dtt off end + device pci 06.0 alias pcie_rp5 off end + device pci 06.1 alias pcie_rp6 off end + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 1 on end + end + end + device pci 0a.0 alias crashlog on end + device pci 0b.0 alias npu off end + device pci 0c.0 alias iaa on end + device pci 0d.0 alias tcss_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port0 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port1 off end + end + end + end + end + device pci 0d.2 alias tcss_dma0 off end + device pci 0e.0 alias vmd off end + device pci 10.0 alias thc0 off end + device pci 10.1 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.1 alias p2sb2 hidden end + device pci 12.6 alias gspi0a off end + device pci 13.0 alias heci_1 off end + device pci 13.1 alias heci_2 off end + device pci 13.2 alias heci_3 off end + device pci 14.0 alias xhci on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + end + end + end + device pci 14.2 alias pmc_shared_sram off end + device pci 14.3 alias cnvi_wifi off end + device pci 14.7 alias cnvi_bluetooth off end + device pci 14.5 alias ieh off end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 on end + device pci 16.1 alias heci2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias ufs off end + device pci 18.0 alias eheci1 off end + device pci 18.1 alias eheci2 off end + device pci 18.2 alias eheci3 off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias soc_espi on end + device pci 1f.1 alias p2sb hidden end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias npk off end + end +end diff --git a/src/soc/intel/pantherlake/elog.c b/src/soc/intel/pantherlake/elog.c index 7750058be4f7..5abf766fc7ee 100644 --- a/src/soc/intel/pantherlake/elog.c +++ b/src/soc/intel/pantherlake/elog.c @@ -36,6 +36,7 @@ static void pch_log_rp_wake_source(void) { PCI_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, { PCI_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, { PCI_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, +#if CONFIG(SOC_INTEL_PANTHERLAKE) { PCI_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, { PCI_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, { PCI_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, @@ -44,6 +45,7 @@ static void pch_log_rp_wake_source(void) { PCI_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, { PCI_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, #endif +#endif }; for (size_t i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); i++) { @@ -62,7 +64,9 @@ static void pch_log_pme_internal_wake_source(void) { PCI_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, { PCI_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, { PCI_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, +#if CONFIG(SOC_INTEL_PANTHERLAKE) { PCI_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, +#endif }; const struct xhci_wake_info xhci_wake_info[] = { { PCI_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index cac866f39ab7..f45d333032e7 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -119,6 +119,7 @@ static const struct slot_irq_constraints irq_constraints[] = { FIXED_INT_PIRQ(PCI_DEVFN_DPTF, PCI_INT_A, PIRQ_A), }, }, +#if CONFIG(SOC_INTEL_PANTHERLAKE) { .slot = PCI_DEV_SLOT_IPU, .fns = { @@ -127,15 +128,21 @@ static const struct slot_irq_constraints irq_constraints[] = { FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A), }, }, +#endif { .slot = PCI_DEV_SLOT_PCIE_2, .fns = { +#if CONFIG(SOC_INTEL_WILDCATLAKE) + FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), +#else FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), #if CONFIG(SOC_INTEL_PANTHERLAKE_H) FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), #endif +#endif }, }, { @@ -143,8 +150,10 @@ static const struct slot_irq_constraints irq_constraints[] = { .fns = { ANY_PIRQ(PCI_DEVFN_TBT0), ANY_PIRQ(PCI_DEVFN_TBT1), +#if CONFIG(SOC_INTEL_PANTHERLAKE) ANY_PIRQ(PCI_DEVFN_TBT2), ANY_PIRQ(PCI_DEVFN_TBT3), +#endif }, }, { @@ -201,7 +210,7 @@ static const struct slot_irq_constraints irq_constraints[] = { ANY_PIRQ(PCI_DEVFN_CSE_4), }, }, -#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) +#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE)) { .slot = PCI_DEV_SLOT_UFS, .fns = { @@ -224,10 +233,12 @@ static const struct slot_irq_constraints irq_constraints[] = { FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), +#if CONFIG(SOC_INTEL_PANTHERLAKE) FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), +#endif }, }, { @@ -789,7 +800,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { efi_uintn_t logo, blt_size; uint32_t logo_size; diff --git a/src/soc/intel/pantherlake/include/soc/iomap.h b/src/soc/intel/pantherlake/include/soc/iomap.h index 0bd56975a902..fac9c03f1cde 100644 --- a/src/soc/intel/pantherlake/include/soc/iomap.h +++ b/src/soc/intel/pantherlake/include/soc/iomap.h @@ -86,6 +86,10 @@ #define IOM_BASE_SIZE 0x10000 #define IOM_BASE_ADDR_MAX 0x401080ffff /* ((IOM_BASE_ADDR + IOM_BASE_SIZE) - 1) */ +/* Temporary MMIO address for GMADR (aka LMEMBAR) with 256MB */ +#define GMADR_BASE 0xB0000000 +#define GMADR_SIZE 0x10000000 + /* I/O port address space */ #define ACPI_BASE_ADDRESS 0x1800 #define ACPI_BASE_SIZE 0x100 diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h index a69f4820c8b6..dc7130cbb50f 100644 --- a/src/soc/intel/pantherlake/include/soc/pci_devs.h +++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h @@ -33,6 +33,12 @@ #define PCI_DEV_IPU _PCI_DEV(IPU, 0) #define PCI_DEV_SLOT_PCIE_2 0x06 +#if CONFIG(SOC_INTEL_WILDCATLAKE) +#define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_2, 0) +#define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_2, 1) +#define PCI_DEV_PCIE5 _PCI_DEV(PCIE_2, 0) +#define PCI_DEV_PCIE6 _PCI_DEV(PCIE_2, 1) +#else #define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0) #define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1) #define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2) @@ -41,6 +47,7 @@ #define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1) #define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2) #define PCI_DEV_PCIE12 _PCI_DEV(PCIE_2, 3) +#endif #define PCI_DEV_SLOT_TBT 0x07 #define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x)) @@ -48,11 +55,11 @@ #define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0) #define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1) #define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2) -#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) +#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) #define PCI_DEV_TBT0 _PCI_DEV(TBT, 0) #define PCI_DEV_TBT1 _PCI_DEV(TBT, 1) #define PCI_DEV_TBT2 _PCI_DEV(TBT, 2) -#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) +#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) #define PCI_DEV_SLOT_TELEMETRY 0x0a #define PCI_DEVFN_TELEMETRY _PCI_DEVFN(TELEMETRY, 0) @@ -143,7 +150,7 @@ #define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) #define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) -#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) +#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE)) #define PCI_DEV_SLOT_UFS 0x17 #define PCI_DEVFN_UFS _PCI_DEVFN(UFS, 0) #define PCI_DEV_UFS _PCI_DEV(UFS, 0) @@ -170,19 +177,23 @@ #define PCI_DEVFN_PCIE2 _PCI_DEVFN(PCIE_1, 1) #define PCI_DEVFN_PCIE3 _PCI_DEVFN(PCIE_1, 2) #define PCI_DEVFN_PCIE4 _PCI_DEVFN(PCIE_1, 3) +#if CONFIG(SOC_INTEL_PANTHERLAKE) #define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_1, 4) #define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_1, 5) #define PCI_DEVFN_PCIE7 _PCI_DEVFN(PCIE_1, 6) #define PCI_DEVFN_PCIE8 _PCI_DEVFN(PCIE_1, 7) +#endif #define PCI_DEV_PCIE1 _PCI_DEV(PCIE_1, 0) #define PCI_DEV_PCIE2 _PCI_DEV(PCIE_1, 1) #define PCI_DEV_PCIE3 _PCI_DEV(PCIE_1, 2) #define PCI_DEV_PCIE4 _PCI_DEV(PCIE_1, 3) +#if CONFIG(SOC_INTEL_PANTHERLAKE) #define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4) #define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5) #define PCI_DEV_PCIE7 _PCI_DEV(PCIE_1, 6) #define PCI_DEV_PCIE8 _PCI_DEV(PCIE_1, 7) +#endif #define PCI_DEV_SLOT_SIO2 0x1e #define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0) diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index 604e7af1b221..cacbab83ad52 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -18,7 +18,11 @@ static const struct pcie_rp_group tbt_rp_groups[] = { }; static const struct pcie_rp_group ptl_rp_groups[] = { +#if CONFIG(SOC_INTEL_WILDCATLAKE) + { .slot = PCI_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, +#else { .slot = PCI_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, +#endif #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) { .slot = PCI_DEV_SLOT_PCIE_2, .count = 4, .lcap_port_base = 1 }, #else diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 0356c3e8ddf9..0061c10ae810 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -511,7 +511,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { size_t logo_size; supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index c3400b45c93f..35562d1a697b 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -682,6 +682,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SiSkipSsidProgramming = 0; mainboard_silicon_init_params(params); + + /* Runtime configuration of S0ix */ + config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable); } /* diff --git a/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/MemInfoHob.h deleted file mode 100644 index 989bfb1a954a..000000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/MemInfoHob.h +++ /dev/null @@ -1,315 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - -@copyright - Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> - - SPDX-License-Identifier: BSD-2-Clause-Patent - -@par Specification Reference: -**/ -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 2 -#define MAX_CH 4 -#define MAX_DIMM 2 -// Must match definitions in -// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h -#define HOB_MAX_SAGV_POINTS 4 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -// @todo remove and use the MdePkg\Include\Pi\PiHob.h -#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) -#ifndef __HOB__H__ -typedef struct _EFI_HOB_GENERIC_HEADER { - UINT16 HobType; - UINT16 HobLength; - UINT32 Reserved; -} EFI_HOB_GENERIC_HEADER; - -typedef struct _EFI_HOB_GUID_TYPE { - EFI_HOB_GENERIC_HEADER Header; - EFI_GUID Name; - /// - /// Guid specific data goes here - /// -} EFI_HOB_GUID_TYPE; -#endif -#endif - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef __MRC_BOOT_MODE__ -#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h - #ifndef INT32_MAX - #define INT32_MAX (0x7FFFFFFF) - #endif //INT32_MAX -typedef enum { - bmCold, ///< Cold boot - bmWarm, ///< Warm boot - bmS3, ///< S3 resume - bmFast, ///< Fast boot - MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. - MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. -} MRC_BOOT_MODE; -#endif //__MRC_BOOT_MODE__ - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR5 -#define MRC_DDR_TYPE_DDR5 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR5 -#define MRC_DDR_TYPE_LPDDR5 2 -#endif -#ifndef MRC_DDR_TYPE_LPDDR4 -#define MRC_DDR_TYPE_LPDDR4 3 -#endif -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 4 -#endif - -#define MAX_PROFILE_NUM 7 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported - -#define MAX_TRACE_REGION 5 -#define MAX_TRACE_CACHE_TYPE 2 - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay -} MRC_IP_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz - UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. -} CONTROLLER_INFO; - -typedef struct { - UINT64 BaseAddress; ///< Trace Base Address - UINT64 TotalSize; ///< Total Trace Region of Same Cache type - UINT8 CacheType; ///< Trace Cache Type - UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code - UINT8 Rsvd[2]; -} PSMI_MEM_INFO; - -/// This data structure contains per-SaGv timing values that are considered output by the MRC. -typedef struct { - UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s - MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec - MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific -} HOB_SAGV_TIMING_OUT; - -/// This data structure contains SAGV config values that are considered output by the MRC. -typedef struct { - UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. - UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. - HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; -} HOB_SAGV_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT8 IsDMBRunning; ///< Deprecated. - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - /// - /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. - /// Bit 0: XMP Profile 1 capability status - /// Bit 1: XMP Profile 2 capability status - /// Bit 2: XMP Profile 3 capability status - /// Bit 3: User Profile 4 capability status - /// Bit 4: User Profile 5 capability status - /// - UINT8 XmpProfileEnable; - UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed - UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - UINT32 VddqVoltage[MAX_PROFILE_NUM]; - UINT32 VppVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; - UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 - UINT32 NumPopulatedChannels; ///< Total number of memory channels populated - HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. - UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels - BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population - BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config - BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - <b>Revision 1:</b> - - Initial version. - <b>Revision 2:</b> - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT64 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; - PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; - PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; - BOOLEAN MrcBasicMemoryTestPass; -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ |