diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/superio/acpi/pnp.asl | 145 | ||||
| -rw-r--r-- | src/superio/acpi/pnp_config.asl | 84 | ||||
| -rw-r--r-- | src/superio/acpi/pnp_generic.asl | 169 | ||||
| -rw-r--r-- | src/superio/acpi/pnp_kbc.asl | 225 | ||||
| -rw-r--r-- | src/superio/acpi/pnp_uart.asl | 134 |
5 files changed, 757 insertions, 0 deletions
diff --git a/src/superio/acpi/pnp.asl b/src/superio/acpi/pnp.asl new file mode 100644 index 000000000000..ba3882a619b9 --- /dev/null +++ b/src/superio/acpi/pnp.asl @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ACPI_PNP_DEFS_ASL +#define SUPERIO_ACPI_PNP_DEFS_ASL + +#define _SUPERIO_ID(name, ldn) name ## ldn +#define SUPERIO_ID(name, ldn) _SUPERIO_ID(name, ldn) + +#define STRINGIFY(x) #x +#define EXPAND_AND_STRINGIFY(x) STRINGIFY(x) +#define SUPERIO_UID(name, ldn) \ + EXPAND_AND_STRINGIFY(SUPERIO_CHIP_NAME-SUPERIO_ID(name, ldn)) +#define SUPERIO_NAME(name) EXPAND_AND_STRINGIFY(SUPERIO_CHIP_NAME name) + +/* Some longer identifiers for readability */ +#define PNP_ADDR_REG ADDR +#define PNP_DATA_REG DATA +#define PNP_LOGICAL_DEVICE LDN +#define PNP_DEVICE_ACTIVE ACTR +#define PNP_IO0_HIGH_BYTE IO0H +#define PNP_IO0_LOW_BYTE IO0L +#define PNP_IO1_HIGH_BYTE IO1H +#define PNP_IO1_LOW_BYTE IO1L +#define PNP_IRQ0 IRQ0 +#define PNP_IRQ1 IRQ1 +#define PNP_DMA0 DMA0 + +#define CONFIG_MODE_MUTEX CMMX +#define ENTER_CONFIG_MODE ENCM +#define EXIT_CONFIG_MODE EXCM +#define SWITCH_LDN SWLD +#define PNP_NO_LDN_CHANGE 0xff + +/* Values for ACPI's _STA method */ +#define DEVICE_NOT_PRESENT 0x00 +#define DEVICE_PRESENT_ACTIVE 0x0f +#define DEVICE_PRESENT_INACTIVE 0x0d + + +/* ================== Generic Method bodies ================= */ + +#define PNP_GENERIC_STA(LDN) \ + ENTER_CONFIG_MODE (LDN)\ + If (PNP_DEVICE_ACTIVE) {\ + Store (DEVICE_PRESENT_ACTIVE, Local0)\ + }\ + Else\ + {\ + Store (DEVICE_PRESENT_INACTIVE, Local0)\ + }\ + EXIT_CONFIG_MODE ()\ + Return (Local0)\ + +#define PNP_GENERIC_DIS(LDN) \ + ENTER_CONFIG_MODE (LDN)\ + Store (Zero, PNP_DEVICE_ACTIVE)\ + EXIT_CONFIG_MODE ()\ + + +/* + * Current power state (returns the chip's state) + */ +#define PNP_DEFAULT_PSC \ + Store(^^_PSC (), Local0)\ + Return (Local0) + +/* + * Current power state (returns the chip's state, if it's in + * power saving mode, 1 if this LDN is in power saving mode, + * 0 else) + * + * PM_REG Identifier of a register which powers down the device + * PM_LDN The logical device number to access the PM_REG + * bit + */ +#define PNP_GENERIC_PSC(PM_REG, PM_LDN) \ + Store(^^_PSC (), Local0)\ + If (Local0) { Return (Local0) }\ + ENTER_CONFIG_MODE (PM_LDN)\ + Store (PM_REG, Local0)\ + EXIT_CONFIG_MODE ()\ + If (Local0) { Return (1) }\ + Else { Return (0) }\ + +/* Disable power saving mode */ +#define PNP_GENERIC_PS0(PM_REG, PM_LDN) \ + ENTER_CONFIG_MODE (PM_LDN)\ + Store (Zero, PM_REG)\ + EXIT_CONFIG_MODE () + +/* Enable power saving mode */ +#define PNP_GENERIC_PS1(PM_REG, PM_LDN) \ + ENTER_CONFIG_MODE (PM_LDN)\ + Store (One, PM_REG)\ + EXIT_CONFIG_MODE () + + +/* ==================== Resource helpers ==================== */ + +#define PNP_READ_IO(IO_FROM, RESOURCE_TEMPLATE, IO_TAG) \ + CreateWordField (RESOURCE_TEMPLATE, IO_TAG._MIN, IO_TAG##I)\ + CreateWordField (RESOURCE_TEMPLATE, IO_TAG._MAX, IO_TAG##A)\ + Or (ShiftLeft (IO_FROM##_HIGH_BYTE, 8), IO_FROM##_LOW_BYTE, Local0)\ + Store (Local0, IO_TAG##I)\ + Store (Local0, IO_TAG##A) + +#define PNP_READ_IRQ(IRQ_FROM, RESOURCE_TEMPLATE, IRQ_TAG) \ + CreateWordField (RESOURCE_TEMPLATE, IRQ_TAG._INT, IRQ_TAG##W)\ + ShiftLeft (One, IRQ_FROM, IRQ_TAG##W) + +#define PNP_READ_DMA(DMA_FROM, RESOURCE_TEMPLATE, DMA_TAG) \ + CreateWordField (RESOURCE_TEMPLATE, DMA_TAG._DMA, DMA_TAG##W)\ + ShiftLeft (One, DMA_FROM, DMA_TAG##W) + +#define PNP_WRITE_IO(IO_TO, RESOURCE, IO_TAG) \ + CreateWordField (RESOURCE, IO_TAG._MIN, IO_TAG##I)\ + Store (And(IO_TAG##I, 0xff), IO_TO##_LOW_BYTE)\ + Store (ShiftRight(IO_TAG##I, 8), IO_TO##_HIGH_BYTE) + +#define PNP_WRITE_IRQ(IRQ_TO, RESOURCE, IRQ_TAG) \ + CreateWordField (RESOURCE, IRQ_TAG._INT, IRQ_TAG##W)\ + Subtract (FindSetLeftBit (IRQ_TAG##W), 1, IRQ_TO) + +#define PNP_WRITE_DMA(DMA_TO, RESOURCE, DMA_TAG) \ + CreateWordField (RESOURCE, DMA_TAG._DMA, DMA_TAG##W)\ + Subtract (FindSetLeftBit (DMA_TAG##W), 1, DMA_TO) + +#endif diff --git a/src/superio/acpi/pnp_config.asl b/src/superio/acpi/pnp_config.asl new file mode 100644 index 000000000000..79dca9f86ad4 --- /dev/null +++ b/src/superio/acpi/pnp_config.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* ======== General PnP configuration functions ======= */ + +/* + * Controlled by the following preprocessor defines: + * PNP_ENTER_MAGIC_1ST If defined, specifies the first magic byte + * used to enter config mode. + * PNP_ENTER_MAGIC_2ND If defined, specifies the second magic byte + * used to enter config mode. + * PNP_ENTER_MAGIC_3RD If defined, specifies the third magic byte + * used to enter config mode. + * PNP_EXIT_MAGIC_1ST If defined, specifies the first magic byte + * used to exit config mode. + */ + + +/* + * Mutex for accesses to the configuration ports (prolog and + * epilog commands are used, so synchronization is useful) + */ +Mutex(CONFIG_MODE_MUTEX, 1) + +/* + * Enter configuration mode (and aquire mutex) + * Method must be run before accesssing the configuration region. + * Parameter is the LDN which should be accessed. Values >= 0xFF mean + * no LDN switch should be done. + */ +Method (ENTER_CONFIG_MODE, 1) +{ + Acquire (CONFIG_MODE_MUTEX, 0xFFFF) +#ifdef PNP_ENTER_MAGIC_1ST + Store (PNP_ENTER_MAGIC_1ST, PNP_ADDR_REG) +#ifdef PNP_ENTER_MAGIC_2ND + Store (PNP_ENTER_MAGIC_2ND, PNP_ADDR_REG) +#ifdef PNP_ENTER_MAGIC_3RD + Store (PNP_ENTER_MAGIC_3RD, PNP_ADDR_REG) +#endif +#endif +#endif + If (LLess(Arg0, PNP_NO_LDN_CHANGE)) { + Store(Arg0, PNP_LOGICAL_DEVICE) + } +} + +/* + * Exit configuration mode (i.e. release mutex) + * Method must be run after accessing the configuration region. + */ +Method (EXIT_CONFIG_MODE) +{ +#ifdef PNP_EXIT_MAGIC_1ST + Store (PNP_EXIT_MAGIC_1ST, PNP_ADDR_REG) +#endif + Release (CONFIG_MODE_MUTEX) +} + +/* + * Just change the LDN. Make sure that you are in config mode (or + * have otherwise acquired CONFIG_MODE_MUTEX), when calling. + */ +Method (SWITCH_LDN, 1) +{ + Store(Arg0, PNP_LOGICAL_DEVICE) +} diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl new file mode 100644 index 000000000000..f7a9b13099d2 --- /dev/null +++ b/src/superio/acpi/pnp_generic.asl @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* =================== Generic PnP Device =================== */ + +/* + * Generic setup for PnP devices. + * + * Controlled by the following preprocessor defines: + * + * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_PNP_LDN The logical device number on the super i/o + * chip for this device (required) + * SUPERIO_PNP_DDN A string literal that identifies the dos device + * name (DDN) of this device (e.g. "COM1", optional) + * SUPERIO_PNP_PM_REG Identifier of a 1-bit register to power down + * the logical device (optional) + * SUPERIO_PNP_PM_LDN The logical device number to access the PM_REG + * bit (required if SUPERIO_PNP_PM_REG is defined) + * SUPERIO_PNP_IO0 The alignment and length of the first PnP i/o + * resource (comma seperated, e.g. `0x02, 0x08`, + * optional) + * SUPERIO_PNP_IO1 The alignment and length of the second PnP i/o + * resource (comma seperated, e.g. `0x02, 0x08`, + * optional) + * SUPERIO_PNP_IRQ0 If defined, the first PnP IRQ register is enabled + * SUPERIO_PNP_IRQ1 If defined, the second PnP IRQ register is enabled + * SUPERIO_PNP_DMA If defined, the PnP DMA register is enabled + */ + +#include "pnp.asl" + +#ifndef SUPERIO_CHIP_NAME +# error "SUPERIO_CHIP_NAME is not defined." +#endif + +#ifndef SUPERIO_PNP_LDN +# error "SUPERIO_PNP_LDN is not defined." +#endif + +Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) { + Name (_HID, EisaId ("PNP0c02")) /* TODO: Better fitting EisaId? */ + Name (_UID, SUPERIO_UID(PN, SUPERIO_PNP_LDN)) + #ifdef SUPERIO_PNP_DDN + Name (_DDN, SUPERIO_PNP_DDN) + #endif + + Method (_STA) + { + PNP_GENERIC_STA(SUPERIO_PNP_LDN) + } + + Method (_DIS) + { + PNP_GENERIC_DIS(SUPERIO_PNP_LDN) + } + +#ifdef SUPERIO_PNP_PM_REG + Method (_PSC) { + PNP_GENERIC_PSC(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + } + + Method (_PS0) { + PNP_GENERIC_PS0(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + } + + Method (_PS1) { + PNP_GENERIC_PS1(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_LDN) + } +#else + Method (_PSC) { + PNP_DEFAULT_PSC + } +#endif + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { +#ifdef SUPERIO_PNP_IO0 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0) +#endif +#ifdef SUPERIO_PNP_IO1 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1) +#endif +#ifdef SUPERIO_PNP_IRQ0 + IRQNoFlags (IR0) {} +#endif +#ifdef SUPERIO_PNP_IRQ1 + IRQNoFlags (IR1) {} +#endif +#ifdef SUPERIO_PNP_DMA + DMA (Compatibility, NotBusMaster, Transfer8, DM0) {} +#endif + }) + ENTER_CONFIG_MODE (SUPERIO_PNP_LDN) +#ifdef SUPERIO_PNP_IO0 + PNP_READ_IO(PNP_IO0, CRS, IO0) +#endif +#ifdef SUPERIO_PNP_IO1 + PNP_READ_IO(PNP_IO1, CRS, IO1) +#endif +#ifdef SUPERIO_PNP_IRQ0 + PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) +#endif +#ifdef SUPERIO_PNP_IRQ1 + PNP_READ_IRQ(PNP_IRQ1, CRS, IR1) +#endif +#ifdef SUPERIO_PNP_DMA + PNP_READ_DMA(PNP_DMA0, CRS, DM0) +#endif + EXIT_CONFIG_MODE () + Return (CRS) + } + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { +#ifdef SUPERIO_PNP_IO0 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0) +#endif +#ifdef SUPERIO_PNP_IO1 + IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1) +#endif +#ifdef SUPERIO_PNP_IRQ0 + IRQNoFlags (IR0) {} +#endif +#ifdef SUPERIO_PNP_IRQ1 + IRQNoFlags (IR1) {} +#endif +#ifdef SUPERIO_PNP_DMA + DMA (Compatibility, NotBusMaster, Transfer8, DM0) {} +#endif + }) + ENTER_CONFIG_MODE (SUPERIO_PNP_LDN) +#ifdef SUPERIO_PNP_IO0 + PNP_WRITE_IO(PNP_IO0, Arg0, IO0) +#endif +#ifdef SUPERIO_PNP_IO1 + PNP_WRITE_IO(PNP_IO1, Arg0, IO1) +#endif +#ifdef SUPERIO_PNP_IRQ0 + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) +#endif +#ifdef SUPERIO_PNP_IRQ1 + PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1) +#endif +#ifdef SUPERIO_PNP_DMA + PNP_WRITE_DMA(PNP_DMA0, Arg0, DM0) +#endif + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } +} diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl new file mode 100644 index 000000000000..722ca1514a4e --- /dev/null +++ b/src/superio/acpi/pnp_kbc.asl @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* =================== Keyboard Controller ================== */ + +/* + * Just uses the default i/o ports 0x60/0x64, irq 1 (and 12 for PS/2 + * mouse). Do we have any system that needs this configurable? + * + * Controlled by the following preprocessor defines: + * + * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_KBC_LDN The logical device number on the super i/o + * chip for this keyboard controller (required) + * SUPERIO_KBC_PS2M If defined, PS/2 mouse support is included in + * the KBC_LDN. Mouse irq is set at IRQ1 of the + * KBC_LDN. + * SUPERIO_KBC_PS2LDN If defined, specifies a second LDN to configure + * PS/2 mouse support. Mouse irq is set at IRQ0 of + * this LDN. + * SUPERIO_KBC_PS2M and SUPERIO_KBC_PS2LDN are mutually exclusive. + */ + +#include "pnp.asl" + +#ifndef SUPERIO_CHIP_NAME +# error "SUPERIO_CHIP_NAME is not defined." +#endif + +#ifndef SUPERIO_KBC_LDN +# error "SUPERIO_KBC_LDN is not defined." +#endif + +#if defined(SUPERIO_KBC_PS2M) && defined(SUPERIO_KBC_PS2LDN) +# error "SUPERIO_KBC_PS2M and SUPERIO_KBC_PS2LDN are mutually exclusive." +#endif + +Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) { + Name (_HID, EisaId ("PNP0303")) + Name (_UID, SUPERIO_UID(KBD, SUPERIO_KBC_LDN)) + + Method (_STA) + { + PNP_GENERIC_STA(SUPERIO_KBC_LDN) + } + + Method (_DIS) + { + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + Store (Zero, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + #if defined(SUPERIO_KBC_PS2LDN) + Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1) + #elif defined(SUPERIO_KBC_PS2M) + Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1) + #endif + } + + Method (_PSC) { + PNP_DEFAULT_PSC + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + PNP_READ_IO(PNP_IO0, CRS, IO0) + PNP_READ_IO(PNP_IO1, CRS, IO1) + PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + PNP_WRITE_IO(PNP_IO0, Arg0, IO0) + PNP_WRITE_IO(PNP_IO1, Arg0, IO1) + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + #if defined(SUPERIO_KBC_PS2LDN) + Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1) + #elif defined(SUPERIO_KBC_PS2M) + Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1) + #endif + } +} + +#if defined(SUPERIO_KBC_PS2M) +Device (SUPERIO_ID(PS2, SUPERIO_KBC_LDN)) { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_LDN)) + + Method (_STA) + { + Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA ()) + } + + Method (_PSC) { + Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._PSC ()) + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IRQNoFlags (IR1) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + PNP_READ_IRQ(PNP_IRQ1, CRS, IR1) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IRQNoFlags () {12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IRQNoFlags (IR1) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) + PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1) + EXIT_CONFIG_MODE () + } +} +#elif defined(SUPERIO_KBC_PS2LDN) +Device (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN)) { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_PS2LDN)) + + Method (_STA) + { + Store (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA (), Local0) + If (LEqual (Local0, DEVICE_PRESENT_ACTIVE)) { + PNP_GENERIC_STA(SUPERIO_KBC_PS2LDN) + } Else { + Return (Local0) + } + } + + Method (_DIS) + { + ENTER_CONFIG_MODE (SUPERIO_KBC_PS2LDN) + Store (Zero, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } + + Method (_PSC) { + PNP_DEFAULT_PSC + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IRQNoFlags (IR1) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_PS2LDN) + PNP_READ_IRQ(PNP_IRQ0, CRS, IR1) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IRQNoFlags () {12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IRQNoFlags (IR1) {} + }) + ENTER_CONFIG_MODE (SUPERIO_KBC_PS2LDN) + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR1) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } +} +#endif diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl new file mode 100644 index 000000000000..c826106ea87c --- /dev/null +++ b/src/superio/acpi/pnp_uart.asl @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* ========================== UART ========================== */ + +/* + * Generic setup for 16550A compatible UARTs. + * + * Controlled by the following preprocessor defines: + * + * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_UART_LDN The logical device number on the super i/o + * chip for this UART (required) + * SUPERIO_UART_DDN A string literal that identifies the dos device + * name (DDN) of this uart (e.g. "COM1", optional) + * SUPERIO_UART_PM_REG Identifier of a 1-bit register to power down + * the UART (optional) + * SUPERIO_UART_PM_LDN The logical device number to access the PM_REG + * bit (required if SUPERIO_UART_PM_REG is defined) + */ + +#include "pnp.asl" + +#ifndef SUPERIO_CHIP_NAME +# error "SUPERIO_CHIP_NAME is not defined." +#endif + +#ifndef SUPERIO_UART_LDN +# error "SUPERIO_UART_LDN is not defined." +#endif + +Device (SUPERIO_ID(SER, SUPERIO_UART_LDN)) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, SUPERIO_UID(SER, SUPERIO_UART_LDN)) + #ifdef SUPERIO_UART_DDN + Name (_DDN, SUPERIO_UART_DDN) + #endif + + Method (_STA) + { + PNP_GENERIC_STA(SUPERIO_UART_LDN) + } + + Method (_DIS) + { + PNP_GENERIC_DIS(SUPERIO_UART_LDN) + } + +#ifdef SUPERIO_UART_PM_REG + Method (_PSC) { + PNP_GENERIC_PSC(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + } + + Method (_PS0) { + PNP_GENERIC_PS0(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + } + + Method (_PS1) { + PNP_GENERIC_PS1(SUPERIO_UART_PM_REG, SUPERIO_UART_PM_LDN) + } +#else + Method (_PSC) { + PNP_DEFAULT_PSC + } +#endif + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x08, 0x08, IO0) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_UART_LDN) + PNP_READ_IO(PNP_IO0, CRS, IO0) + PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x03f8, 0x03f8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02f8, 0x02f8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03e8, 0x03e8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02e8, 0x02e8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0ff8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00, IO0) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_UART_LDN) + PNP_WRITE_IO(PNP_IO0, Arg0, IO0) + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } +} |