summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Documentation: Fix sphinx warningsMartin Roth2022-05-305-20/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following warnings: mainboard/starlabs/common/flashing.md:: WARNING: image file not readable: - mainboard/starlabs/common/fwupdVersion.png - mainboard/starlabs/common/BiosLock.jpg - mainboard/starlabs/common/SwitchBranch.png cbfstool/index.md:: WARNING: document isn't included in any toctree internals/devicetree_keywords.md:: WARNING: document isn't included in any toctree mainboard/asus/wifigo_v1.md:: WARNING: document isn't included in any toctree mainboard/google/index.md:: WARNING: document isn't included in any toctree mainboard/starlabs/common/flashing.md:: WARNING: document isn't included in any toctree releases/boards_supported_on_branches.md:: WARNING: document isn't included in any toctree WARNING: None:any reference target not found: - releases/coreboot-4.16-relnotes - releases/coreboot-4.15-relnotes - releases/coreboot-4.14-relnotes - releases/coreboot-4.13-relnotes - releases/coreboot-4.12-relnotes - releases/coreboot-4.11-relnotes - releases/coreboot-4.10-relnotes - releases/coreboot-4.9-relnotes - releases/coreboot-4.8.1-relnotes - releases/coreboot-4.7-relnotes - releases/coreboot-4.6-relnotes - releases/coreboot-4.5-relnotes - releases/coreboot-4.4-relnotes - releases/coreboot-4.3-relnotes - releases/coreboot-4.2-relnotes - releases/coreboot-4.1-relnotes - ../../src/soc/intel/common/block/cse/cse.c Change-Id: I22273bc1bc34b6297cef4e594c454c2316d4215a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/brya/var/kinox: Correct the target of DPTF active policyDtrain Hsu2022-05-301-4/+4
| | | | | | | | | | | | | | | Kinox has four temperature sensors. Modify the target of DPTF active policy to map correct temperature sensor. BUG=b:231380286 TEST=Boot to Chrome OS and doesn't see "DPTF: Invalid sensor ID" from ec comsole. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Icb5c285a6f483e2a1b6510a962ff7f7f6e9a79e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/biostar/a68n_5200: Use pci_or_config8()Elyes Haouas2022-05-291-10/+4
| | | | | | | | Change-Id: I4be0a4ad980b4167eaaafc22399b680abf011553 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/lint/checkpatch: Add alloc functions to alloc with multiplies checkElyes Haouas2022-05-291-3/+5
| | | | | | | | | | This reduce difference with linux v5.18. Change-Id: Id9412f7b6c0b9f76b39a094142aaded5c2aa1059 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/lint/checkpatch: Update 'Check for compiler attributes'Elyes Haouas2022-05-291-29/+59
| | | | | | | | | | This reduce difference with linux v5.18. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I817630321587dec515cd94aa7b73a17819526190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/lint/checkpatch.pl: Use 'allocFunctions'Elyes Haouas2022-05-291-3/+14
| | | | | | | | | | This reduce difference with linux v5.18. Change-Id: I1fc71b9cb6a4e4f8b27fbe6d45f4fa4e2c236157 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* cpu/x86: Allow SoC to select the LAPIC access modeSubrata Banik2022-05-291-0/+12
| | | | | | | | | | | | | Intel Meteor Lake SoC expects to select x2APIC for accessing LAPIC hence, this patch provides an option where SoC code choose the correct LAPIC access mode using choice selection. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I39c99ba13ad6e489c300bd0d4ef7274feeca9d4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/brya: Increase Resizable BAR address space limit to 32 bitsTim Wawrzynczak2022-05-291-0/+4
| | | | | | | | | | | | | | | | | The dGPU used for some Brya projects requests 32 bits of address space for one of its BARs via the Resizable BAR mechanism. This Kconfig is currently set at 29 bits for brya, so the allocation currently is capped at 29 bits. This patch sets the limit to 32 bits for brya boards, which is enough for the GPU. BUG=b:214443809 TEST=all of the dGPU PCI BARs on agah can be successfully allocated Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I61dbe47f1f316967d052bae748ff23babde61ef0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* device: Add IORESOURCE_ABOVE_4G flag to PCI64 resourcesTim Wawrzynczak2022-05-291-1/+3
| | | | | | | | | | | | | | | When a PCI resource is marked as 64-bits, the IORESOURCE_ABOVE_4G flag needs to be passed to the v4 allocator to ensure that the resource will be allocated in a range large enough to succeed. BUG=b:214443809 TEST=agah can successfully allocate all of the Nvidia GN20 BARs Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3f16f52f2a64f8728853df263da29871dca533f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/google/brya/var/agah: Fix GPU power sequencingTim Wawrzynczak2022-05-292-13/+55
| | | | | | | | | | | | | | | | | | | | | | While testing the power sequencing code for the GPU, a few mistakes were found. This patch fixes those errors: 1) FBVDD load-switch enable is active-low 2) NVVDD VR enable is active-high 3) GPU_PERST_L should be driven low during GPIO table programming 4) The BAR saving code missed the top 32 bits of 64-bit BARs 5) sequence_rail() assumed the pwr_en_gpio and pg_gpio were the same polarity 6) PEG vGPIOs were not programmed to the correct NF BUG=b:233552225 TEST=dGPU is able to successfully enumerate over PCIe bus Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I85767d382012a0c7dfdb1f849768e0160f06c273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/variants/felwinter: Enable Bluetooth offload supportMac Chiang2022-05-293-0/+50
| | | | | | | | | | | | | | | Add fw_config support NMAX98360_ALC5682VS_I2S_2WAY and I2S2 vgpio config and enabling cnvi_bt_audio_offload UPD bit. BUG=none TEST=emerge-brya coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I64a4e5479905911b2e9d1597b78131720abb689e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* payloads/external: Add support for coreDOOM payloadNicholas Chin2022-05-288-0/+101
| | | | | | | | | | | | | | | | | | coreDOOM is a port of DOOM to libpayload, based on the doomgeneric source port. It renders the game to the coreboot linear framebuffer, and loads WAD files from CBFS. Tested with QEMU i440fx/q35 and a Dell Latitude E6400 using the libgfxinit provided linear framebuffer. Project page: https://github.com/nic3-14159/coreDOOM Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: Ice0403b003a4b2717afee585f28303c2f5abea5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* payloads/tianocore: Fix unclean working directory detectionNicholas Chin2022-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit ae48b42683 (payloads/tianocore: Init submodules), Tianocore's Makefile no longer detects an unclean working directory and thus always performs a `git checkout`, overwriting any uncommited changes made in the cloned sources. The change of "clean" to "dirty" effectively inverts the logic of the if-else condition, which would normally swap the two possible code paths of the branch. However, since `git status` outputs multiple lines, most of which do not contain "clean", the -v option (select non-matching lines) causes grep to always match at least 1 line and thus return success. This causes the if-else branch containing the `git checkout` to always be taken regardless of the state of the working tree, masking the issue of the inverted logic. Removing the -v option addresses both of these issues and restores the intended behavior of the if-else block. TEST: 1) Build coreboot successfully with the Tianocore UefiPayloadPkg option. 2) Make a change in the cloned Tianocore sources that results in an unclean working directory and check for the "Working directory not clean" message when building coreboot. Change-Id: Icd4952b40c147d0fba676089ced5a8b59b93ad50 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/starlabs/lite/glk: Remove unnecessary DPTF UPDSean Rhodes2022-05-281-2/+0
| | | | | | | | | | | The default for DPTF is off (0), so remove the entry that sets this to off. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0397ff6f71766a2f738ab2b71be298ef8f2b1c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/starlabs/lite/{glk/glkr}: Remove unnecessary parametersSean Rhodes2022-05-282-70/+0
| | | | | | | | | | | Since using FSP 2.2.0.0, the defaults match the required settings so they no longer need to be specified. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie0e00cae67cb89b184392e97b8ec196d45ea5d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* util/inteltool: Add support for Alder Lake chips detection and GPIOsMichał Kopeć2022-05-286-0/+807
| | | | | | | | | | | | | | Add PCI IDs for Alder Lake H devices and their GPIO tables. PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362). TEST=dump GPIOs on i5-12600K with Z690 chipset Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* mb/google/brya/var/agah: Update USB-C port settingIvy Jian2022-05-281-2/+2
| | | | | | | | | | | | | | | | | Correct the USB-C port setting according to schematics. AP log: port C0 DISC req: usage 1 usb3 3 usb2 1 port C1 DISC req: usage 1 usb3 1 usb2 3 BUG=b:233554817 BRANCH=brya TEST=emerge-draco coreboot chromeos-bootimage Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Iea4aee19dff8e0bc863be46532f89e81f52f281b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/mithrax: Update typeC EC mux portJohn Su2022-05-281-5/+5
| | | | | | | | | | | | | | | | | | | We need to put USB setting in mux order. BUG=b:234103724 TEST=Type C mux configuration is correct. Wrong: added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Correct: added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f8dbee35159960d17107e23fcde825a38c7de4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/common: Use coreboot error codesSridhar Siricilla2022-05-282-4/+4
| | | | | | | | | | | | | The patch uses coreboot error codes instead of uint8_t data type in the pre_mem_debug_init function. TEST=build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I957ff764900cb789bf2aacf0472dcb281f48af07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* mb/starlabs/labtop: Add LabTop Mk IIISean Rhodes2022-05-2816-1/+960
| | | | | | | | | | | | | | | | | | | Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iii-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ben McMillen <ben@starlabs.systems>
* ec/starlabs/merlin/kbl: Add required headers for dead_code_tSean Rhodes2022-05-281-0/+3
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia6c3ba80d5e6ac3d4fd8a935732ef7e32cf33998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* abuild: Build with clang only when supportedArthur Heymans2022-05-281-1/+11
| | | | | | | | | | | This changes the behavior of '-L/--clang' to only buildtest when a target has ARCH_SUPPORTS_CLANG set. Change-Id: I362fcd0f795d27f13dde793a79774f08c497bd38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* Kconfig: Mark clang as ready to use on some archArthur Heymans2022-05-282-4/+17
| | | | | | | | | | | | | | | | | | This adds 2 flags: * invisible opt-in flag for platforms on which clang seems to work * visible opt-in flag to allow experimenting Clang seems to work rather well on x86_32 so it makes sense to start adding that to Jenkins buildtesting, which this allows. This allows abuild to differentiate between targets that are known to build with clang. This makes buildtesting just those targets easier. Change-Id: I46f1bad59bda94f60f4a141237ede11f6eb93cc2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* arch/x86/tables.c: Increase MAX_SMBIOS_SIZEArthur Heymans2022-05-281-1/+1
| | | | | | | | | | | | | | | | Systems have a lot more cores now and 4KiB is not cutting it. E.g. for a system with 255 cores more than 16KiB is needed. We could also make this a Kconfig parameter but it's probably not worth having such micro optimizations to save a few KiB. Change-Id: Idd47e55d8d679cc70eae996ee1af3ad7eaa1d0cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Move cbfstool & ifdtool dirs under util\Martin Roth2022-05-287-4/+5
| | | | | | | | Change-Id: If1b263345baf321cde75058f310c96d89a95d62d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* arch/x86/smbios.c: Fix for CONFIG_MAX_CPUS > 255Arthur Heymans2022-05-281-1/+3
| | | | | | | | | Change-Id: I079c99006fea95ba3dc2fb02c95a3747af55e218 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/mp_init.c: Drop 'real' vs 'used' save stateArthur Heymans2022-05-283-39/+13
| | | | | | | | | | | Now that the save state size is handled properly inside the smm_loader there is no reason to make that distinction in the mp_init code anymore. Change-Id: Ia0002a33b6d0f792d8d78cf625fd7e830e3e50fc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* cpu/x86/smm_module_load: Rewrite setup_stubArthur Heymans2022-05-281-71/+21
| | | | | | | | | | | | | | | | | | | This code was hard to read as it did too much and had a lot of state to keep track of. It also looks like the staggered entry points were first copied and only later the parameters of the first stub were filled in. This means that only the BSP stub is actually jumping to the permanent smihandler. On the APs the stub would jump to wherever c_handler happens to point to, which is likely 0. This effectively means that on APs it's likely easy to have arbitrary code execution in SMM which is a security problem. Change-Id: I42ef9d6a30f3039f25e2cde975086a1365ca4182 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* cpu/x86/smm_module_loader: Add a convenient ss_topArthur Heymans2022-05-281-8/+7
| | | | | | | | | | | | | We don't want to keep track of the real smm size all the time. As a bonus now ss_start is now really the start of the save state instead of top - MAX(stub_size, save state size). Change-Id: I0981022e6c0df110d4a342ff06b1a3332911e2b7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* cpu/x86/smm_module_loader.c: Rewrite setupArthur Heymans2022-05-281-176/+135
| | | | | | | | | | | | | | | | This code is much easier to read if one does not have to keep track of mutable variables. This also fixes the alignment code on the TSEG smihandler setup code. It was aligning the code upwards instead of downwards which would cause it to encroach a part of the save state. Change-Id: I310a232ced2ab15064bff99a39a26f745239f6b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* cpu/x86/smm: Drop 'entry' struct elementArthur Heymans2022-05-281-4/+2
| | | | | | | | | | | | This is a duplicate of code_start. Change-Id: I38e8905e3ed940fb34280c939d6f2f1fce8480a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/x86/smm: Refactor creating a stub/save state mapArthur Heymans2022-05-281-42/+32
| | | | | | | | | | | | | This code was very hard to read so rewrite it using as few mutable local variables as possible. Tested on qemu with 128 cores. Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/google/brya/var/volmar: Correct _PLD valuesWon Chung2022-05-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 | MLB DB | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ibd36fb961de9e9af9da1fd885eeb958c833d38bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/taniks: Correct _PLD valuesWon Chung2022-05-281-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia66c6fafe08110b8d8f9a138a2516ae03f8e1809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/{taeko, taeko4es}: Correct _PLD valuesWon Chung2022-05-282-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Icd56c650a03c5db6e1e68e4ca4c9f0c068a7a430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/{primus, primus4es}: Correct _PLD valuesWon Chung2022-05-282-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | A0 C0 | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia493fd28c362d2c0c343c2d121f6611cfd8f7f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/kano: Correct _PLD valuesWon Chung2022-05-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 | | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I840b0f363a1ff304b310505efdaba2ac1cd10472 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/felwinter: Correct _PLD valuesWon Chung2022-05-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | C1 | MLB DB | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ie4f96e3636a8b519923fdba7f9bd07d7a3e1d7ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/64613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/{anahera, anahera4es}: Correct _PLD valuesWon Chung2022-05-282-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ A | | A C0 | MLB DB | C2 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia1e95aba2f7d02131b0b0cdd6c7211a23e355084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/{brya0, brya4es}: Correct _PLD valuesWon Chung2022-05-282-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | A0 C0 | MLB DB | C1 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I68fb940825bfcf7c77ca3015372025e47e7fcc41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* commonlib/timestamp_serialized.h: Fix typosElyes Haouas2022-05-281-6/+6
| | | | | | | | Change-Id: I245af182da5fe0869e834423959e1d040724157a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/nissa: set tcc_offset value to 10Sumeet Pawnikar2022-05-281-0/+2
| | | | | | | | | | | | | | | Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature as mentioned in doc #572349. BUG=b:229804441 BRANCH=None TEST=Build FW and test on Nivviks board Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/sabrina/acpi/soc.asl: re-enable WAL1 call in PNOT methodFelix Held2022-05-281-2/+1
| | | | | | | | | | | | Now that the FSP provides the ALIB ACPI table via a HOB, the PNOT power notify method can call WAL1 which will then call ALIB to communicate the current AC/DC state to the SMU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic966b73aa28f329207f8d840ca5fb5f2bf6ec9b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64667 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Update Kconfig to use Ti50Jon Murphy2022-05-281-1/+1
| | | | | | | | | | | | | | Skyrim uses the Ti50 GSC and the config should be updated to reflect that. BUG=b:233750667 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5d4af19ab2dda35ab687a0659898d79b08c4de97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/starlabs/lite: Add Bluetooth USB interfaceSean Rhodes2022-05-282-0/+4
| | | | | | | | | | Enable the USB port that is used by the Bluetooth interface on the CNVI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a330618c5f1c5fd5e3147cb6307c157b28070ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/64545 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite: Remove webcam USB port from devicetreeSean Rhodes2022-05-284-6/+6
| | | | | | | | | | | Remove the Webcam USB port form the devicetree and handle it solely in devtree, which will enable or disable it based on the CMOS option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c89c7103aca5c3d42215122e9d94c83947b6fee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* ec/starlabs/merlin/glk: Add Trackpad enable/disable Q eventsSean Rhodes2022-05-281-0/+12
| | | | | | | | | | | | | | | | Add Q60 and Q61 events to disable or enable the trackpad. The support for this Q event was added in Star Labs EC version 1.11 Add Q events Q60 and Q61 which are bound to the F10 key. The event is select based on the value of 0x14, 0x11 will send Q60 and 0x22 will send Q61. Q60 will pull GPIO_177 to low, consequently disabling the trackpad and Q61 will reset it to the default configuration. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I091b0eb268d4d6d2109559765be71e2746b85f54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlite/lite: Configure tcc_offset based on power_profile settingsSean Rhodes2022-05-281-6/+9
| | | | | | | | | | | Set tcc_offset value based on the power_profile value, ranging from 5 to 15 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id30bec9c095517884a7361226aed703b370f2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/mediatek/mt8192: Enable thermal hardware resetRex-BC Chen2022-05-282-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | Under the current watchdog setting, the system will not reboot when the temperature is too high. To enable thermal hardware reset, we need to enable thermal control request and set it to reboot mode. Note that because thermal throttle (by lowering cpu frequency) is currently enabled, the thermal hardware reset shouldn't be triggered under normal circumstances. This feature is only for new hardware structure for thermal. Therefore, we only need to apply it on MT8192/MT8195/MT8186. This setting is based on thermal and watchdog section of MT8192 Function Specification. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I98b062c2070384527624c3bcf0dfded25a2c8ce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64676 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Enable thermal hardware resetRex-BC Chen2022-05-281-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Under the current watchdog setting, the system will not reboot when the temperature is too high. To enable thermal hardware reset, we need to enable thermal control request and set it to reboot mode. Note that because thermal throttle (by lowering cpu frequency) is currently enabled, the thermal hardware reset shouldn't be triggered under normal circumstances. This feature is only for new hardware structure for thermal. Therefore, we only need to apply it on MT8192/MT8195/MT8186. This setting is based on thermal and watchdog section of MT8195 Function Specification. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia6489bb953d148a43af173454d6f2b3e2a1dfcf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64675 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 14:51:02 +0000