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* soc/intel/common/block/sata: Fix scope for SATA ACPI deviceMatt DeVillier2024-02-181-1/+1
| | | | | | | | | | | | | | | | | | | | | acpi_device_path() includes the device name, so we end up with: Scope (\_SB.PCI0.SATA) { Device (SATA) { ... Fix this by using acpi_device_scope() instead. TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify SATA device scope correct. Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/*: Add SPDX headers for cmos.default filesMartin Roth2024-02-1894-0/+188
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc: Add SPDX license headers to Kconfig filesMartin Roth2024-02-18122-0/+241
| | | | | | | | | | Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/samsung to mb/up: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1880-0/+152
| | | | | | | | Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/opencellular to mb/roda: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1851-0/+102
| | | | | | | | | Change-Id: Ia2100d26027a7f71739d5445f781b52c517ed966 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80594 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/inventec to mb/ocp: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1871-0/+142
| | | | | | | | Change-Id: Ib1bbf22480783f63fc2d729b94251e755d2f1720 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80593 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth2024-02-18156-0/+311
| | | | | | | | | Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/cavium to mb/foxcomm: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1842-0/+84
| | | | | | | | Change-Id: Ib100a677935cf3309a380952c35e9060e64433cb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/51nb to mb/bytedance: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1859-0/+118
| | | | | | | | | Change-Id: I71dc3dd270b9a61c86b59031f898af37f0fea345 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80590 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec, lib, security, sb: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1824-1/+47
| | | | | | | | Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers: Add SPDX license headers to Kconfig filesMartin Roth2024-02-18100-0/+200
| | | | | | | | Change-Id: Ib27894f0f1e03501583fffb2c759b493d6a7b945 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80588 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch to cpu: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1841-0/+81
| | | | | | | | Change-Id: I7dd7b0b7c5fdb63fe32915b88e69313e3440b64a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80587 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* payloads: Add SPDX headers to KconfigMartin Roth2024-02-1823-0/+46
| | | | | | | | | Change-Id: Iea569fd457b3cd1f4746fbc6a96319eb42733a6b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80586 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* LICENSES: Add LGPL 2.1 licenseMartin Roth2024-02-181-0/+175
| | | | | | | | | | This is used in util/cbfstool/elf.h and lzmadecode. Change-Id: I75e71259f23bee602ffb54b0c51e0e4a9da3f8e5 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* Treewide: Fix incorrect SPDX license stringsMartin Roth2024-02-1845-45/+45
| | | | | | | | | | | These strings didn't match the license names exactly, so update them to match. Change-Id: Ib946eb15ca5fa64cbd6b657350b989b4a4c1b7b7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/prodrive/hermes: Use chipset dt reference namesFelix Singer2024-02-181-41/+41
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I81dd67fd200768942fe355180b75db0746cda8ea Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/rex: Do not power on FPMCU in ramstagePatryk Duda2024-02-173-6/+6
| | | | | | | | | | | | | | | | | | | | | When 'reset_gpio' and 'enable_gpio' properties are defined in overridetree.cb, the kernel will power on the FPMCU. If the device was previously enabled the kernel will reset it. To avoid situation in which the FPMCU is powered on and reset later we leave the FPMCU powered off in coreboot and started by the kernel. This is exactly what other boards do (e.g. brya). TEST=Boot the board (e.g. karis) and make sure the FPMCU was booted once (e.g. examine FPMCU console logs) Change-Id: I5df8d9385be2621c02ccee2d36511a4e80ab87d1 Signed-off-by: Patryk Duda <patrykd@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intelblocks/systemagent: Add missing N6005 Jasper Lake SKU to PCI ID listMichał Żygowski2024-02-171-0/+1
| | | | | | | | Change-Id: I3fb4c6cfe24290c34682ff1c3396540465048727 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/jasperlake/bootblock: Report missing Jasper Lake SKUMichał Żygowski2024-02-171-0/+1
| | | | | | | | Change-Id: Ie0d25eca75225ab33e6c15ef5ccb9073151f4148 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/brox: Handle bluetooth enable on devicesAshish Kumar Mishra2024-02-172-6/+10
| | | | | | | | | | | | | | | | | For devices that require CNVi Bluetooth select WIFI_BT_CNVI in FW_CONFIG. Discrete Bluetooth devices need to select WIFI_BT_PCIE. BUG=b:319188820,b:325084796 BRANCH=None TEST=Boot image on SKU1,SKU2 and check BT devices enumerate. Change-Id: Iba008682fcfa7ddc1ec400649c8742c721666f1d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80564 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPICShelley Chen2024-02-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting the EC interrupt GPIO as an APIC is able to solve many problems that we are currently seeing: 1. Routing through the APIC make the IRQ# associated with this pin unavailable to claim for other devices in the kernel. This is causing EC interrupts to not work. 2. Since EC interrupt are not working, we are not able to flash the EC from the DUT. 3. Also, the GPI_INT configuration does not allow us to set the polarity of the GPIO, which means that it is by default set as active high. As a result, we are seeing an excessive number of host command interrupts to the EC. This disappears when we change the configuration to APIC and set the polarity as INVERT. BUG=b:319129926,b:324707182 BRANCH=None TEST=1. After boot up, check if ec_cros_lpcs driver was successfully registered. Look for the following string: "cros_ec_lpcs GOOG0004:00: Chrome EC device registered" 2. Make sure can flash the EC image from the DUT 3. Make sure EC console is not getting continuous stream of host commands. Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80467 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.corp-partner.google.com>
* soc/intel/mtl: Double the `IgdDvmt50PreAlloc` UPD size to 128MBSubrata Banik2024-02-161-2/+2
| | | | | | | | | | | | | | This patch increases the IgdDvmt50PreAlloc value as per Intel recommendation starting with GFX PEIM 103x. TEST=Able to build and boot google/rex. Change-Id: I236b38a1ac5efbfcd23e373c09204d8a07b97618 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80406 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/common/tcss: Rename tcss_mux_init to disconnect_tcss_devicesSean Rhodes2024-02-151-2/+2
| | | | | | | | | | | | | | Rename tcss_mux_init to disconnect_tcss_devices to make it clear what this function is doing, as it doesn't initialise anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79874 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/starlabs/starbook/rpl: Configure PMC muxSean Rhodes2024-02-151-0/+11
| | | | | | | | | | | | | | Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I580b148b036e62fbcab50d1ca2ab1ed021cfed6b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/adl: Configure PMC muxSean Rhodes2024-02-151-0/+11
| | | | | | | | | | | | | | Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I9e49612d7f165a9c9604093535f7b141a4c7048c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79426 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin: Remove ubtc.aslSean Rhodes2024-02-152-52/+0
| | | | | | | | | | Remove the ubtc.asl as it's no longer needed. Change-Id: I8564bb7d9bd94c8303c543c078bc76192539c5f2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80484 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin: Remove the CMOS Bank 1 entriesSean Rhodes2024-02-151-16/+0
| | | | | | | | | | These entries no longer exist as they are stored in CFR. Change-Id: Ia85855fddc36db76a65490a1d685e1943db28b74 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mainboard/qemu-aarch64: Map entire RAM space as read-write memoryAlper Nebi Yasak2024-02-151-2/+1
| | | | | | | | | | | | | | | | | | | | | Commit 977b8e83cb0a ("mb/emulation/qemu-aarch64: Add MMU support") adds MMU support for ARM64 QEMU VMs, but registers a limited 1GiB region for the DRAM, with a note that ramstage should update it. However on recent versions of QEMU "virt" VMs, accessing RAM outside this registered region results in an exception even if the address is backed by actual RAM. This interferes with RAM detection which catches these exceptions, effectively limiting us to detecting a maximum 1GiB of RAM even if more is available. Register the entire RAM space to MMU instead of just the 1GiB, so that probing RAM addresses can correctly detect how much RAM we have. Change-Id: I3afbd27b91ab37304a29a62506f965ac3cfb1c06 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* util/ifdtool.c: Fix long_options for platformVojtech Vesely2024-02-151-1/+1
| | | | | | | | | | | Platform has argument, but has_arg was mistakenly set to 0. Change-Id: I7d5c31c2b1da544cb73d9e213d463332fcdba7df Signed-off-by: Vojtech Vesely <vojtech.vesely@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80432 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
* mb/lenovo/x230: Disable the USB P8 portAlexei Sorokin2024-02-151-1/+1
| | | | | | | | | | | | | | | | This port is not connected on the X230, X230i, X230t. When X230 support was introduced and pei_data was filled in, this port was disabled, but after commit 3dc12c1e1918 (bd82x6x: Consolidate early native USB init) it has become enabled. Change-Id: I952193798c0894b256b21d9fb3f238074ff5f0f0 Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80468 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop unused soft_reserved_ram_resource macroFelix Held2024-02-141-3/+0
| | | | | | | | | | | | The unused soft_reserved_ram_resource expanded to the non-existent fixed_mem_resource function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b454175c6530e539aa24dffb771368b0aea6da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/dedede/Kconfig.name: Alphabetize board listingMatt DeVillier2024-02-141-54/+54
| | | | | | | | Change-Id: I7230bb8f9883f186c10f41132a2919c3fd99f8c1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/dedede/Kconfig: Alphabetize selections for baseboardsMatt DeVillier2024-02-141-8/+8
| | | | | | | | Change-Id: I245eb8a9961e3e0025c0275f306a4d989b532331 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80491 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/Kconfig: Alphabetize variant board listingsMatt DeVillier2024-02-141-139/+139
| | | | | | | | Change-Id: I2909375d38c37332293bd7928ae33d5bb502694f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80490 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/showdevicetree: drop unmaintained toolFelix Held2024-02-144-159/+0
| | | | | | | | | | | | | This tool doesn't have a makefile, when trying to compile it manually with the given instructions it even fails to compile after fixing the paths in the given command, and it references the non-existing PCI_BUS_SEGN_BITS Kconfig symbol, so just drop this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79934 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drv/gfx/generic: Add Intel ACPI Backlight funcs for LCD devicesMatt DeVillier2024-02-141-0/+36
| | | | | | | | | | | | | | | | Normally this would be done by the Intel GMA driver, but we can't have two copies of the _DOD method, so generate the LCD backlight controls here to allow use of this driver instead of the default GMA panel definition. TEST=build/boot Win11 on google/byra (redrix), ensure ACPI brightness controls functional. Change-Id: Ic8fbaf7550405f8c6f36012c8efadb8c36b968c2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80061 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Add VBTs and select INTEL_GMA_HAVE_VBTMatt DeVillier2024-02-1420-0/+19
| | | | | | | | | | Vbt data files extracted from dedede recovery image 120.0.6099.272. Change-Id: I28485d501e519cdaa06c55c20eba07190c5c6b6f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/starlabs/starbook/kbl: Remove tcc_offset entrySean Rhodes2024-02-141-3/+0
| | | | | | | | | | | The TCC offset is configured in devtree.c, so remove it from the devicetree. Change-Id: I044a68854cc142b057cf31b4e2456d2ad1d0dd3a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/starlabs/merlin: Remove the call to pc_keyboard_initSean Rhodes2024-02-141-2/+0
| | | | | | | | | | As DRIVERS_PS2_KEYBOARD isn't set, this function is not doing anything. Change-Id: Ie8842a32fca56f330a0f044cf96112dc5cae6546 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Documentation/vboot: Update vboot supported boards listMatt DeVillier2024-02-141-10/+12
| | | | | | | | | | Auto-generated by util/vboot_list/vboot_list.sh. Change-Id: I35dc51915c8468543c981e1b046e4ecf8d5b4bbf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* tree; Remove unused <lib.h>Elyes Haouas2024-02-148-8/+0
| | | | | | | | | Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80433 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/x230: introduce EDP variantAlexander Couzens2024-02-145-6/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a modification for the x230 which uses the 2nd DP from the dock as the integrated panel's connection, which allows using a custom eDP panel instead of the stock LVDS display. There are several adapter boards present on the market and all of them use the same method of enabling the custom eDP panel. To make this work with coreboot, the internal LVDS connector should be disabled in libgfxinit. Additionally, VBT has been modified to keep brightness controls functional on the adapter boards that use LVDS for the job. The modifications done to the VBT are: - Remove the LVDS port entry. - Move the DP-3 (which is the 2nd DP on the dock) entry to the first position on the list. - Set the DP-3 as internally connected. This has been reported to work with the following panels: - LP125WF2-SPB4 (1920*1080, 12.5") - LQ125T1JW02 (2560*1440, 12.5") - LQ133M1JW21 (1920*1080, 13.3") - LTN133HL10-201 (1920*1080, 13.3") - B133HAN04.6 (1920*1080, 13.3") - B133QAN02.0 (2560*1600, 13.3") Other eDP panels not on this list should work as well. Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mainboard: Enforce usage of AZALIA_ARRAY_SIZESNicholas Sudsgaard2024-02-1311-22/+11
| | | | | | | | | | | This is the de facto method and should be enforced to keep things consistent. Change-Id: I7eee77f7fd49bc38e27cb0e6be0a4a6555098cc7 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/clevo/tgl-u: Use enum for AZALIA_PIN_CFG misc fieldNicholas Chin2024-02-131-11/+11
| | | | | | | | | | | | | Use the new JACK_PRESENCE_DETECT and NO_JACK_PRESENCE_DETECT enums instead of raw values in the misc field of AZALIA_PIN_CFG. TEST: Timeless build for clevo/tgl-u did not change Change-Id: Ic3f4128ecbf89ddce3b6e705ebef76da343a433c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* include/device/azalia_device.h: Add enum for misc fieldNicholas Chin2024-02-131-2/+7
| | | | | | | | | | | | | | | | The HDA specification defines bits 11:8 of the Configuration Default register as a miscellaneous field for other jack information. Only bit 8 has a standard meaning, and indicates that the jack does not have presence detect capability. Add an enum for use in the AZALIA_PIN_DESC macro to indicate this field. Note that many vendor firmwares set bits 11:9 to non zero values despite them being reserved in the specification, and their meaning in these cases is not well known. Change-Id: I70cbfca8541828a1e0c7280887060c04e4c71721 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/*: Replace use of gfx/generic addr field with display typeMatt DeVillier2024-02-1328-32/+32
| | | | | | | | | | | | | | | Eliminates the use of a magic number, and the resulting DID entry in the _DOD method is the same. TEST=build/boot google/drallion, dump SSDT and verify DID entry is unchanged. Change-Id: Ic929cf7ec6849ba398653226bbe46d27b4e3fa81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* drivers/gfx/generic: Add display type fieldMatt DeVillier2024-02-132-2/+24
| | | | | | | | | | | | | | | | | | | | Add an enum for the Display Type, which if set, can be used to generate the Device ID value dynamically when the addr field is not set. This will allow devicetree entries to specify the display type instead of a hex value for the address which requires referencing the ACPI spec to decode. For an internal panel connected to the first port on the graphics chip, currently an addr value of 0x80010400 is specified. Replacing the 'addr' field with the 'type' field and setting it to 'panel' will generate the same DID value. Change-Id: Id0294a14606b410a13fa22eeb240df9e409a7ca3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/brox: Set display output type for eDP panelMatt DeVillier2024-02-131-0/+1
| | | | | | | | | | | | | Set the display type for the LCD panel configured via the gfx/generic driver. This will ensure the correct DID/device address are generated in the SSDT. Change-Id: If63374329ed5eb4330517ca1bf2ba1ada24fa54a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80244 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: Use name 'LCD0' for internal panel outputMatt DeVillier2024-02-131-1/+1
| | | | | | | | | | | | | The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. Change-Id: Id52f7c0e542423ba08eeed89bf9b171e540e10e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/rex: Use name 'LCD0' for internal panel outputMatt DeVillier2024-02-132-2/+2
| | | | | | | | | | | | | The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. Change-Id: Id93cfea93edfefc8237b53214734531b811b36e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80202 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 05:59:34 +0000