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* util/ifdtool: Add coreboot build system supportPatrick Georgi2021-01-122-4/+19
* soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`Angel Pons2021-01-122-2/+1
* Documentation: Fix toctree and remove dead linksPatrick Rudolph2021-01-124-6/+4
* Documentation: Add known bugs of x86_64 code on real hardwarePatrick Rudolph2021-01-121-0/+30
* cpu/x86/sipi_vector: Simplify loop getting unique CPU numberPatrick Rudolph2021-01-121-3/+2
* device/pci_device.c: Use same indents for switch/caseFelix Singer2021-01-121-1/+1
* util/superiotool: Add IT8720F EC registersMichael Büchler2021-01-121-0/+29
* soc/intel/common/pcie: Add helper function for getting mask of enabled portsFurquan Shaikh2021-01-123-0/+58
* device: Use __pci_0_00_0_config in config_of_soc()Furquan Shaikh2021-01-122-5/+13
* soc/intel/alderlake: Add PCH ID 0x5182Subrata Banik2021-01-123-1/+4
* drivers/genesyslogic/gl9763e: Add HS400ES compatibility settingsBen Chuang2021-01-122-0/+9
* mb/google/zork/var/vilboz: Fix FW_CONFIG_SHIFT_WWAN valueJohn Su2021-01-121-1/+1
* cpu/intel/haswell: Add delay for TPM before Flex Ratio rebootAngel Pons2021-01-111-0/+5
* cpu/intel/haswell: Allow tuning VR for C-state operationsAngel Pons2021-01-112-2/+50
* cpu/intel/haswell: Raise PSI1 threshold to 20AAngel Pons2021-01-111-1/+1
* cpu/intel/haswell: Enable turbo ratio if availableAngel Pons2021-01-111-4/+7
* cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSRAngel Pons2021-01-111-6/+0
* libpayload/lpgcc: Drop redundant linker pathNico Huber2021-01-111-1/+1
* libpayload/lpgcc: Set proper include paths for in-tree buildsNico Huber2021-01-111-6/+11
* libpayload/lpgcc: Add more variables to support in-tree buildsNico Huber2021-01-111-6/+12
* mb/google/octopus: add audio codec into SSFC support for MeepTony Huang2021-01-113-0/+23
* drivers/genesyslogic/gl9763e: Fix boot on eMMC failed issue on VolteerRenius Chen2021-01-112-0/+16
* soc/intel/{icl,tgl,jsl,ehl}: add LPIT supportMichael Niewöhner2021-01-118-0/+12
* soc/intel/skl: add SLP_S0 residency register and enable LPIT supportMichael Niewöhner2021-01-112-0/+2
* soc/intel/cnl: add SLP_S0 residency register and enable LPIT supportMichael Niewöhner2021-01-112-0/+3
* acpi,soc/intel/common: add support for Intel Low Power Idle TableMichael Niewöhner2021-01-117-1/+182
* {soc,vc,mb}/intel: Drop support for Cannon Lake SoCFelix Singer2021-01-1136-8033/+0
* mb/google/volteer: Add CSE Lite SKU support to DrobitWayne3_Wang2021-01-111-0/+1
* util/sconfig: Emit chip config pointers for PCI devices on root busFurquan Shaikh2021-01-111-5/+20
* soc/amd/cezzane: Add a minimal chipset treeFurquan Shaikh2021-01-112-0/+9
* util/sconfig: Change __pci*|__pnp* device pointers to constFurquan Shaikh2021-01-111-4/+4
* soc/intel/common/uart: Use simple(_s_) variants of PCI functionsFurquan Shaikh2021-01-111-41/+34
* soc/intel/uart: Drop SoC callback `soc_uart_console_to_device`Furquan Shaikh2021-01-1110-194/+49
* soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-SJeremy Soller2021-01-111-0/+47
* mb/google/volteer: Set FORCE_PWR low at boot timeJohn Zhao2021-01-114-4/+4
* soc/amd/picasso: Separate GPIO define into gpio_defs.hEric Lai2021-01-113-244/+250
* vc/intel/FSP2_0/CPX-SP: update to FSP ww01 releaseJonathan Zhang2021-01-1110-214/+10
* vendorcode/intel/fsp: Update Tiger Lake v3444 FSP HeadersSrinidhi N Kaushik2021-01-111-8/+20
* mb/emulation/qemu: Copy page tables to DRAM in assemblyPatrick Rudolph2021-01-116-2/+91
* mb/google/dedede/var/magolor: Remove the unused touch controllerRen Kuo2021-01-111-15/+0
* soc/intel/cannonlake: Enable wake from USB in S4Patrick Rudolph2021-01-111-1/+4
* nb/intel/gm45: Guard macro parametersAngel Pons2021-01-101-39/+39
* nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parametersAngel Pons2021-01-101-1/+1
* device: Add new Kconfig VGA_ROM_RUN_DEFAULT for mainboard userSubrata Banik2021-01-101-2/+9
* mb/intel/adlrvp: Update GPIOs as per latest schematicsSubrata Banik2021-01-101-7/+7
* mb/intel/adlrvp: Fix FW download failed for PEG 060, 010Subrata Banik2021-01-101-2/+8
* soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPsSubrata Banik2021-01-105-21/+42
* soc/intel/broadwell: Use `mp_cpu_bus_init`Angel Pons2021-01-103-5/+2
* superiotool/nuvoton: Set NCT6791D GPIO inputs to NANANico Huber2021-01-101-3/+3
* cpu/intel/haswell/haswell.h: Align with BroadwellAngel Pons2021-01-103-55/+51
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