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* soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya2021-08-125-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch configures the SKU specific power delivery parameters for the VR domains. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADLV Sowmya2021-08-121-0/+34
| | | | | | | | | | | | | | | | | | | | | | | This patch updates the VccIn Aux Imon IccMax for ADL-P to SOC SKU specific values from the FSP default value 160. * ADL-P 682(45W) = 137. * ADL-P 482(28W) = 128. * ADL-P 282(15W) = 128. These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56176 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: add 4Gb and 6Gb dram densityJamie Chen2021-08-122-0/+8
| | | | | | | | | | | | | | | | This patch adds 4gb and 6gb dram density support to APL and GLK. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: Ic0d5d14f26a30da7a9caf4ef43d7fac88a4d2bf1 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55153 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: change LPDDR4 density enum definitionJamie Chen2021-08-122-31/+25
| | | | | | | | | | | | | | | | | | Originally we use rank_density=0 to mean disable the channel, but actually rank_density=0 means 4Gb density in the FSP. This patch changes the LPDDR4 enum values to the real density number and adds a switch statement to mapping the density define in the FSP. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: I36dba2cef130211e7aea9e2a4f82c5db78f82a83 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56805 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/system76/*: Add CMOS option tableTim Crawford2021-08-1215-0/+205
| | | | | | | | | | | | | | | | | | System76 uses several custom CMOS values downstream. Reduce our diff by providing a generic layout with the defaults: boot_option=Fallback debug_level=Debug power_on_after_fail=Enable Tested on galp3-c, gaze15, oryp5, oryp6. All boards boot multiple times with USE_OPTION_TABLE selected. Change-Id: Ie57b0e5713bba8ad46e1a4123a3ddd43e0eea964 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/mediatek/mt8192: move DFD driver to common folderRex-BC Chen2021-08-126-14/+22
| | | | | | | | | | | | | Move DFD driver to common folder so MT8195 can also use it. BUG=b:192429713 TEST=emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7937cddf5f3a66f9269a94301d3134e6f4f9f22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore settingRyan Chuang2021-08-121-3/+4
| | | | | | | | | | Remove the unnecessary Vcore setting for the DVFS feature. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If3c28e57a559a7ec04319c1a489138817e44ec4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: revise the dependency of DVFS config optionsRex-BC Chen2021-08-122-1/+2
| | | | | | | | | | | | The MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT only makes sense if DVFS is enabled (e.g., MEDIATEK_DRAM_DVFS) so we should change it to depend on that instead of selecting DVFS. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib81e4e48e863616ed1e36cd5c0000f4e2cfb5456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* drivers/generic/alc1015: Add HID to support alc1019Eric Lai2021-08-122-3/+6
| | | | | | | | | | | | | | ALC1019 will use the ACPI compatible and share the same driver with ALC1015. Add HID to support more compatible ICs. BUG=b:195891240 TEST=ALC1019P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3e98297f3a39048b24d61e61ca95c60cd2037eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* libpayload: Mark Intel 300 series AHCI as testedNico Huber2021-08-121-0/+1
| | | | | | | | | | | | Tested with filo on roda/rw14. Change-Id: Ia5f868d3a9cead0a872e6d3e9fdacd6eeb7f158b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56666 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add Maxim Polyakov as intelp2m maintainerMaxim Polyakov2021-08-121-0/+5
| | | | | | | | | | | Change-Id: I85835712926ca456b108b1d80e6a55f75e604591 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/dedede/var/galtic: Add charger throttling functionFrankChu2021-08-121-1/+9
| | | | | | | | | | | | | | | | | | | | Add charger current throttling support for galtic control charger index * 64 = Value mA 32*64=2048 28*64=1792 24*64=1536 20*64=1280 BUG=b:187231627 TEST=Built and tested on boten system Cq-Depend: chrome-internal:3846209 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I5e1849551ff051bca591f19f9e40da4c89ab74e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/dedede/variants/haboki: add discrete TPM in overridetreeWisley Chen2021-08-121-4/+9
| | | | | | | | | | | | | | | Haboki is project which use discrete TPM, so add discrete TPM and disable cr50 in overrideree. BUG=b:187094464 TEST=FW_NAME=haboki emerge-keeby coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I08f2a562c3f62c60402350151ea260b70890a744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-STim Crawford2021-08-121-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. TGL also introduces parameters for customizing the default SVID:SSID. These must be set or it will still use the FSP defaults. Tested by checking lspci output on System76 darp7 (TGL-U). References: - b1fa231d76a ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S") - TigerLake FSP Integration Guide - Intel Document #631120-001 Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/variants/redrix: enable LTE PCIe portWisley Chen2021-08-121-0/+3
| | | | | | | | | | | | | | | Enable LTE PCIe port according to fw config. BUG=b:192052098 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ic9472d2249c622858a75c63bc82e8e4e8166a3d7 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56894 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/redrix: add mipi camera supportWisley Chen2021-08-122-0/+73
| | | | | | | | | | | | | | | Add mipi camera support by selecting the Kconfig symbols and adding it to the devicetree with ACPI UID 0x50000 and name IPU0. BUG=b:192052098 TEST=checked mipi camera works Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I69281f36ddbc1abf9905c8db9287500f9aa995c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56893 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/gimble: Update GPIO for PP1800 DMIC enableMark Hsieh2021-08-121-0/+2
| | | | | | | | | | | | | | add GPP_D16 in gimle gpio.c and set value to 1 for PP1800 DMIC init sequence BUG=b:195968649 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ia0639162e2c3f02f622470fa16c21fe8a067cf7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56889 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add Tim Crawford as a maintainer for System76Tim Crawford2021-08-121-0/+2
| | | | | | | | | Change-Id: I8aa9ee1627bf319660b193b4602d8c2d0b562424 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52580 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/trogdor: Add new variant WormdinglerZanxi Chen2021-08-123-0/+6
| | | | | | | | | | | | | | New board introduced to trogdor family. BUG=b:193870279 BRANCH=none TEST=make Change-Id: If3d9662e8725e30e1308d77b05545efbee29f846 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/variant/taeko: Update devicetree settingsJoey Peng2021-08-111-2/+277
| | | | | | | | | | | | | | Based on schematic and gpio table of taeko, generate overridetree.cb settings for taeko. BUG=b:195494281 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Implement report_cache_info() functionSubrata Banik2021-08-111-0/+18
| | | | | | | | | | | | | | Make use of deterministic cache helper functions from Alder Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384 Cache size = 12 MiB Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* arch/x86: smbios write 7 table using deterministic cache functionsSubrata Banik2021-08-111-34/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes use of deterministic cache helper functions, for example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper functions from arch/x86/cpu_common.c file. Also, changed argument for get_number_of_caches() function that receives cpu_get_max_cache_share() data directly. Drop unused variables partitions, cache_line_size and number_of_sets as struct cpu_cache_info.size would provide the cache size directly. TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output. Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0005, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 288 kB Maximum Size: 288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Data Associativity: 12-way Set-associative Handle 0x0006, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 192 kB Maximum Size: 192 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Instruction Associativity: 8-way Set-associative Handle 0x0007, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE2 Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Unknown Location: Internal Installed Size: 1280 kB Maximum Size: 1280 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: Unknown Handle 0x0008, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE3 Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 12288 kB Maximum Size: 12288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: 12-way Set-associative Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* arch/x86: Helper functions to get deterministic cache parametersSubrata Banik2021-08-112-0/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates helper function that internally detects the CPU type (AMD or Intel) and pick the leaf to send CPUID instruction with different cache level to retrieve deterministic cache parameters. Lists of helper functions generated as part of this CL : 1. cpu_check_deterministic_cache_cpuid_supported => if CPU has support for deterministic cache using CPUID instruction. 2. cpu_get_cache_ways_assoc_info => Get cache ways for associativity. 3. cpu_get_cache_type => Get cache type. 4. cpu_get_cache_level => Get cache level. 5. cpu_get_cache_phy_partition_info => Get cache physical partitions. 6. cpu_get_cache_line_size => Get cache line size. 7. cpu_get_cache_sets => Get cache number of sets. 8. cpu_is_cache_full_assoc => Check if cache is fully associative. 9. cpu_get_max_cache_share => Cores are sharing this cache. 10. get_cache_size => Calculate the cache size. 11. fill_cpu_cache_info => Fill cpu_cache_info structure. Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/cret: Fix DPTF passive and critical policiesDtrain Hsu2021-08-101-0/+36
| | | | | | | | | | | | | | | | | | TSR2 thermal sensor doesn't define in cret. Fix DPTF passive and critical policies for getting negative temperatures in OS. BUG=b:195868075 BRANCH=dedede TEST=Build and boot to OS in cret. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I849662cbb3adc8e528d65af2c90e7c8e4880d607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/intel/adlrvp: create dynamic power limits mechanism for thermalSumeet Pawnikar2021-08-104-0/+76
| | | | | | | | | | | | | | | | | | Add dynamic power limits selection mechanism for aldrvp board. BUG=None BRANCH=None TEST=Build FW and test on adlrvp with DPTF tool On adlrvp (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (55000, 55000) On adlrvp (682): Overriding DPTF power limits PL1 (5000, 45000) PL2 (115000, 115000) Change-Id: Id1aef0125c6e1e105665172f19bda271e232d94f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/variants/primus: Remove DPTF fan controlScott Chao2021-08-101-32/+0
| | | | | | | | | | | | | BUG=b:195901486, b:195387997 BRANCH=none TEST=Check fan is able to control by EC Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If758d75ff24c88c9eaf0de90ac0ef08d172a2edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56879 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/system76/oryp6: Enable TAS5825M smart ampTim Crawford2021-08-104-1/+1795
| | | | | | | | | | | | | | | | Allows using the internal speakers of the oryp6. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I57781a7223a52b8fc5295cf686412926529c3a7f Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cbMAULIK V VAGHELA2021-08-105-8/+2
| | | | | | | | | | | | | | | | | | For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/brya/adlrvp: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA2021-08-104-12/+6
| | | | | | | | | | | | | | | | | | | | | coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/hatch/scout: Update DPTF parametersKenneth Chan2021-08-101-8/+10
| | | | | | | | | | | | | | | update the DPTF parameters received from the thermal team. BUG=b:195602767 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I5dc89d1d4c2b64c9aac780a7db743a91fd0ebc9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jeff Chase <jnchase@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codecSunwei Li2021-08-103-2/+63
| | | | | | | | | | | | | | | | | Compatible headphone codec "Realtek ALC5682I-VD" and "cirrus CS42L42" Compatible AMP codec "ALC1015Q-VB" and "MAX98360" BUG=b:193373320 BRANCH=dedede TEST=Both realtek and cirrus audio codec can work normally Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I9121e75eaf46b43e6dc5ef2e31029a153c7a807d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* mb/google/brya/variant/taeko: Update memory settingsJoey Peng2021-08-105-13/+113
| | | | | | | | | | | | | Based on the Taeko's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4e23c28aaf20d9e52b43033b4e41c751e26872bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/storo: Fixed iasl can not run on DutTao Xia2021-08-091-1/+1
| | | | | | | | | | | | | | | | | | The TSR1._PSV has been redefined. It will report errors when disassembling the ACPI tables with the iasl. It is OK when Removing the TSR1._PSV and adding the TSR0._PSV BUG=b:194509417 BRANCH=dedede TEST=The iasl can run on Dut successfully Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I524255c79d3c71573d122944da5058389f79d95d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Evan Green <evgreen@chromium.org>
* mb/intel/adlrvp: Support VBT binaries for LP4 and LP5Bernardo Perez Priego2021-08-091-0/+3
| | | | | | | | | | | | | | | This will enable to include multiple VBT binaries in a single image and load corresponding file according to HW configuration. BUG=None TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iace0e5e0783b2074393a537da8cc645102d2acda Reviewed-on: https://review.coreboot.org/c/coreboot/+/55969 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe SlotAamir Bohra2021-08-091-6/+6
| | | | | | | | | | | | | | | Keep the clock source for PCIe slots as always on. Also turn off the unused (0/1/5/6) clock sources. Currently bilby only uses clock sources 2, 3 and 4, out of which clock source 3 and 4 are routed for PCIe external slot. And clock source 2 is routed for M.2 PCIe slot. TEST:Verify end devices enumerate on D:F 1.1/1.2 RPs over warm reboot. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: Ida485b06279b0a8659c8d00873c3d6023d1e542f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56826 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools/lp4x: Update READMETim Wawrzynczak2021-08-091-9/+10
| | | | | | | | | | | The lp4x spd_tools also support Alder Lake (ADL), so update the the README to reflect this fact. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iedb1ea1c3558e5f179feac2c725667db5b327b2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests/Makefile.inc: Add function wrapping mechanismJakub Czapiga2021-08-091-1/+18
| | | | | | | | | | | | | | | This patch extends mocks functionality to allowing wrapping of mocked functions. Original function name will be prefixed with `__real_`. Example: - Mocked function: cbfs_lookup() - New function name: __real_cbfs_lookup() - Mock name: cbfs_lookup() Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I7cd0d66a17029955cbf75c8b155a7ebb7f5513aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56719 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/taeko: Configure GPIOs according to schematicsJoey Peng2021-08-092-0/+184
| | | | | | | | | | | | | Update initial gpio configuration for taeko BUG=b:195252436 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/variants/brya0: set power limits for thermalSumeet Pawnikar2021-08-092-0/+19
| | | | | | | | | | | | | | | | | | | Set power limits for brya0 variant board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 variant board with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I4c07319af756b10e5d22f320e97ff956fb4a14c6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56622 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* gimble: enable elan touchscreenScott Chao2021-08-091-6/+6
| | | | | | | | | | | | | | Enable Elan touchscreen and remove Goodix touchscreen. We also get confirmation by Elan that address is 0x15. BUG=b:195494292 BRANCH=none TEST=build coreboot and dmesg | grep hid, it showed i2c-ELAN9050:00. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I20a7fd0b370803c14990b77bab302727af197ccb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56801 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4Tim Wawrzynczak2021-08-091-1/+1
| | | | | | | | | | | The code is clearer when ACPI_DEVICE_SLEEP_D3_COLD is used instead of the number 4. Change-Id: I4b0ade1cd0b4b9cdb59f90f8d455269d0b69ed86 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* drivers/uart/acpi: Update _S0W return value to D3hotTim Wawrzynczak2021-08-091-1/+1
| | | | | | | | | | | | | | | | In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most UARTs that do have wake capabilities support wake from D3hot rather than D3cold. BUG=b:187228954 TEST=compile Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* drivers/spi/acpi: Update _S0W return value to D3hotTim Wawrzynczak2021-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most SPI peripherals that do have wake capabilities support wake from D3hot rather than D3cold. This also allows coreboot to expose a power resource to perform power sequencing for a SPI peripheral that is intended to retain power in S3/S0ix. If support for a device with d3cold wake support is needed, it could be added in later as an option. BUG=b:187228954 TEST=compile Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* drivers/i2c/da7219: Update _S0W to D3hotTim Wawrzynczak2021-08-091-1/+1
| | | | | | | | | | | | | | The DA7219 does not support wake from D3cold, therefore update the return value of _S0W from D3cold to D3hot. BUG=b:187228954 TEST=compile Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/brya: create dynamic power limits mechanism for thermalSumeet Pawnikar2021-08-094-0/+67
| | | | | | | | | | | | | | | | | | | Add dynamic power limits selection mechanism for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* elogtool: add to gitignoreJack Rosenthal2021-08-091-0/+1
| | | | | | | | | | | | Add the binary output of the new elogtool to the .gitignore, so that running "make -C util/cbfstool" keeps the tree clean. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I806338a4b33abbc3d55e4edef2736c19d56fa005 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Quesada <ricardoq@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/system76/oryp6: Drop DIMM_SPD_SIZETim Crawford2021-08-091-4/+0
| | | | | | | | | | | The board uses the default size specified in the SoC. Change-Id: Ie71a0fea1ff9de6c4f1ce8db2db09bb3cd35d04d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* MAINTAINERS: Add System76 as maintainer for TAS5825MTim Crawford2021-08-091-0/+6
| | | | | | | | Change-Id: I302e408fa9479e7fc03f344f092e145dd2b86ba5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52581 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA2021-08-092-6/+2
| | | | | | | | | | | | | | | | | | | | | | coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpusMAULIK V VAGHELA2021-08-091-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot always assumes that BSP APIC ID will always be 0 but as per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, it says that BSP can be any processor whose index/APIC ID might not be 0. To handle this situation, init_cpu call is required to modify to handle dynamic detection of APIC ID from BSP instead of hardcoding always through devicetree. Function has been updated to create a new node with actual BSP APIC ID when devicetree doesn't contain APIC ID defined. In case APID ID is defined, function will use a node with the APIC ID defined in devicetree. Changes also requires to remove "lapic 0" hardcoding from devicetree to allow code to fill BSP APIC ID dynamically. Otherwise coreboot will create an extra node for CPU with APIC ID 0 and it'll show as a extra node in kernel. This will cause kernel to report wrong (extra) core count information then actually present. BUG=None BRANCH=None TEST=Boot the JSL system and observe there is no functional impacts. Without this CL kernel core count in `lscpu` = 3 With this CL, kernel core count is corrected to 2. Change-Id: Ib14a5c31b3afb0d773284c684bd1994a78b94445 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 18:47:00 +0000