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* Replace hlt with halt()Patrick Georgi2014-12-02125-177/+92
| | | | | | | | | | | | | | | | | | There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* build system: remove ROMSTAGE_ELF variablePatrick Georgi2014-12-022-20/+7
| | | | | | | | | | | | No need to keep that just because x86 has one extra linking step. Change-Id: Iffdbf64e0613f89070ed0dfb009379f5ca0bd3c1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7611 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* tianocoreboot: Update config to make it compileMarcel Meißner2014-12-021-34/+57
| | | | | | | | | Change-Id: Ie584460529dcd342702dc00787df9c20e2ef10e7 Signed-off-by: Marcel Meißner <mm-meissner@gmx.de> Reviewed-on: http://review.coreboot.org/7541 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* nvramtool: cmos_read(): Use malloc() instead of alloca()Andrew Engelbrecht2014-12-021-1/+4
| | | | | | | | | | | | | | | Fixes crash occurring when 'nvramtool -a' tried to free a prematurely freed pointer. (Tested on x60) malloc() is correct because the pointer is accessed outside the calling function. The pointer is freed in the parent function list_cmos_entry(). Change-Id: I1723f09740657f0f0d9e6954bd6d11c0a3820a42 Signed-off-by: Andrew Engelbrecht <sudoman@ninthfloor.org> Reviewed-on: http://review.coreboot.org/7620 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Add UCB RISCV support for architecture, soc, and emulation mainboard..Ronald G. Minnich2014-12-0145-2/+2379
| | | | | | | | | | | | | | | | Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* Mark non-executable files non-executablePatrick Georgi2014-12-0135-0/+0
| | | | | | | | | | | | No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* 3rdparty: Update to latest commit in blobs repositoryPaul Menzel2014-12-011-0/+0
| | | | | | | | | | | | Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support binary AGESA release), which is the latest commit in the blobs repository. Change-Id: I3d643f7565700272c22b59ed764c3269801f4413 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7595 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* gigabyte/ga-b75m-d3h: Add new Intel mainboardDamien Zammit2014-11-3021-0/+1564
| | | | | | | | | | | | | | | | | | | | | | | | | This is based on LENOVO X230 port. Board boots to linux via SATA or USB. All USB ports are working. Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS. Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7341 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* gcc.c: Test for gcc, not for non-clangPatrick Georgi2014-11-301-1/+1
| | | | | | | | | | | This is gcc specific, not necessary-everywhere-but-on-clang. Change-Id: Ie02587bd41c856cbf730ea2f72f594a20b5fefbe Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7609 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* buildgcc: support DESTDIR for libelfPatrick Georgi2014-11-301-1/+1
| | | | | | | | | | | | | The libelf build system doesn't support the DESTDIR variable. Work around by mangling prefix when installing. Change-Id: I3a56eb2bf919bcb9b586b945dce26a02dbaff931 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7613 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Unify remaining binutils invocationsPatrick Georgi2014-11-304-48/+8
| | | | | | | | | | | | | No need to pass calls through gcc in one case and directly to binutils in another. Just always call binutils. Change-Id: Icf9660ce40d3c23f96dfab6a73c169ff07d3e42b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7610 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* build system: only do the compiler test for gccPatrick Georgi2014-11-302-9/+9
| | | | | | | | | | | There isn't a history of broken clang compilers yet so let's give it a chance. Change-Id: Iddb63700e3850116313c1ddee69111f936191055 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* Replace hlt() loops with halt()Patrick Georgi2014-11-3025-77/+60
| | | | | | | | Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* Introduce halt()Patrick Georgi2014-11-303-0/+67
| | | | | | | | | | | It's a portable and generic way to halt the system. Useful when waiting for the platform to reset. Change-Id: Ie07f3333d294a4d3e982cbc2ab9014c94b39fce0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7605 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* intel/sandybridge: make sure to stay in HLT until rebootPatrick Georgi2014-11-301-1/+3
| | | | | | | | | | | | It also tells the compiler that we never leave here. Change-Id: I824569efd46b577588387b29fc7781abf8c42385 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7579 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* vendorcode/intel/fsp: Update FSP_VENDORCODE_HEADER_PATHFEI WANG2014-11-292-7/+7
| | | | | | | | | | | | | | Minor change in Kconfig to remove "/" defined in FSP_VENDORCODE_HEADER_PATH and update the path in Makefile.inc. Change-Id: Ic19ab9560aabe307d45b560f167874383cc920aa Signed-off-by: Fei Wang <wangfei.jimei@gmail.com> Signed-off-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-on: http://review.coreboot.org/5894 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mainboard/intel/minnowmax: use Baytrail Gold3 FSPYork Yang2014-11-293-19/+34
| | | | | | | | | | | | | Baytrail Gold3 FSP support memory down configuration. Update Minnow Max to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use different FSP image. Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/7581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
* ec: Use DEVICE_NOOP macro formalism over static stub funcEdward O'Callaghan2014-11-293-42/+6
| | | | | | | | | | | | | | | | | | | | | | The in source comment: /* This function avoids an error on serial console. */ refers to the resource allocator needing to find a non-NULL function pointer else complaints of "... missing read_resources" will be spewed. Unfortunately/fortunately (depending on the time of day) compiler optimisers have gotten a bit better at optimising away no-op functions leading to the very message these stubs attempted to avoid. By using the DEVICE_NOOP formalism that is static inlined 'suggests' (not enforces) to the compiler to keep these symbols around. Change-Id: I182019627b6954a4020f9f70e9c829ce3135f63c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7598 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* i945: make PCIe link wait sensiblePatrick Georgi2014-11-282-5/+6
| | | | | | | | | | | | | | | | | | | | | | Waiting for (a & 4) == 3 to become true proves futile unless you're searching for defective hardware or neutrino impact. While I'm not 100% sure that this is the actual intent (no data-sheets at hand, and the public ones are unhelpful as usual), it's the likely correct version and it's also boot-tested on intel/d945gclf. While at it, replace register number with the name found in the public datasheet. Change-Id: I4b87001967a2013e0089806e8cd606d5ee81b0d9 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6575 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki2014-11-283-5/+2
| | | | | | | | | | | | This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. See commit a0b4a8d. Change-Id: Iae82498ab729df5682d89e66bb9de96457e91619 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7465 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* mainboard/lenovo/g505s/devicetree.cb: Fix duplicate typoEdward O'Callaghan2014-11-281-4/+2
| | | | | | | | | Change-Id: Ic2b8ca54b9a16c13439b3081969deec0b7187e01 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Use AMD_F15_TN_A0 define in FTnLogicalIdTables.cEdward O'Callaghan2014-11-281-1/+1
| | | | | | | | | Change-Id: I6b20ded866fa0418bd24ce9eef3775557c2feec7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7562 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* drivers/i2c/at24rf08c/lenovo_serials.c: Use NULL over '0'Edward O'Callaghan2014-11-281-3/+3
| | | | | | | | | Change-Id: I7d8922d1812814ea2ebd72aaf5b5e28dc592bfb3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7590 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* drivers/i2c/at24rf08c/lenovo_serials.c: Upper-case'ifyEdward O'Callaghan2014-11-281-1/+1
| | | | | | | | | | Thereby making consistent with other i2c drivers Change-Id: I5ddc9d98fbbc1db68a933e3b9a6b92f309b72c41 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7589 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Make acpi_fill_dmar into parameterVladimir Serbinenko2014-11-273-11/+6
| | | | | | | | | Change-Id: I5e237cb7acbf47b2c8a4cd725ee8e16e422e3b17 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7371 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* southbridge/amd/agesa/hudson/pci.c: Use DEVICE_NOOP macroEdward O'Callaghan2014-11-271-4/+1
| | | | | | | | Change-Id: I39edaaed67f45e7c56ec02c2aac2a4c5e1b63bc7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7586 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* mainboard/lenovo/g505s: New port Richland APU A10-5750MEdward O'Callaghan2014-11-2734-0/+3607
| | | | | | | | | | | | | | | | Richland APU A10-5750M 8GB RAM 4MB Flash Boots to working Linux with SeaBIOS payload. S3 works with Linux 3.16.3-2 Debian Jessie. Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7560 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* vendorcode/amd/agesa: Use F15TN AGESA for F15RLEdward O'Callaghan2014-11-272-0/+5
| | | | | | | | | | | | | | | | | For the moment we make use of Trinity f15tn AGESA for Richland f15rl support until we have properly worked out the discrepancies. Adds RL-A1 Richland stepping cpuid to F15TnLogicalIdTables lookup. We later wish to merge f15tn and f15rl support into the AGESA in any case. Change-Id: Ia9070d4e392ce7eb912771d1c7b3ef1440f8e8a8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7559 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
* cpu/amd/agesa/family15rl: Provide Richland CPU supportEdward O'Callaghan2014-11-2711-5/+387
| | | | | | | | | | | | | | Richland - Microarchitecture: Piledriver Core stepping: RL-A1 CPUID: 610F31 Change-Id: I790085fbf36d836c903dcce77d794abb8578712b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7537 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* northbridge/amd/agesa/family15rl: Provide Richland supportEdward O'Callaghan2014-11-2711-2/+1617
| | | | | | | | | | | | Provide our current development support for Richland. We would however like to see a unification of 'northbridge/amd/agesa' instead of another copy-paste merged. Change-Id: I88005939844d1132cfd3531a9d47389320026814 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7536 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* i945: Find memory controller by slot instead of by PCIID.Vladimir Serbinenko2014-11-261-1/+1
| | | | | | | | | | | Slot is the same on all model but PCIID varies. Tested on AOA150. Change-Id: I474548971ea140f25326a68fe8e86698a6725dea Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* ibexpeak: Don't check for CONFIG_HAVE_SMI_HANDLER.Vladimir Serbinenko2014-11-261-2/+2
| | | | | | | | | | | | It's always true for this chipset. Change-Id: Icd7666ed361c33170b1171da9ec46547685b996e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7571 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* sandy/ivy: Remove explicit setting of HAVE_SMI_HANDLER.Vladimir Serbinenko2014-11-269-9/+0
| | | | | | | | | | | | Southbridge already selects it, no need to repeat. Change-Id: I9a5ad553f48e30103371cc2d896168ae4abfb8ef Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7570 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Rewrite board_status in go.Vladimir Serbinenko2014-11-264-0/+794
| | | | | | | | | | | This allows easy creation of redistribuable binary. Change-Id: I12a82d509cd4bd46baeb4f4066e509c69301ab95 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7565 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Export board-status info.Vladimir Serbinenko2014-11-265-0/+30
| | | | | | | | | | | Rather than hunting version across compile tree in board_status, export it by coreboot itself. Change-Id: I7f055e6fc077134001ebdb11df7381bbdc71a1fc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6747 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* agesa/family12: Switch to per-device ACPIVladimir Serbinenko2014-11-266-524/+123
| | | | | | | | Change-Id: I944e35b04612eca8add80c9f546df99a9a930ac8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7036 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* agesa/family16kb: Switch to per-device ACPIVladimir Serbinenko2014-11-264-440/+146
| | | | | | | | Change-Id: I7d9cbbd1aeadecc1a4c91816df303c6cb4817fe3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* agesa/family15tn: Switch to per-device ACPIVladimir Serbinenko2014-11-269-916/+156
| | | | | | | | | Change-Id: Icc2e7b66b3ff5f70b219a3e67494ce3df055c9d5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7033 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* agesa/family15: Switch to per-device ACPIVladimir Serbinenko2014-11-267-770/+139
| | | | | | | | Change-Id: I3847eb1524a5a816cd4885a31d703b410804c1f0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7032 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* agesa/family14: Fix includes for ACPIKyösti Mälkki2014-11-261-2/+1
| | | | | | | | | | Change-Id: Ic4425840a984a7713088a2568e25bae982e22fc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7582 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* agea/family14: Switch to per-device ACPIVladimir Serbinenko2014-11-2511-1854/+131
| | | | | | | | Change-Id: Icc663c28713f2d872bfeb1749303ce92db953bf5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7031 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* lenovo/t60: Remove PIRQ table.Vladimir Serbinenko2014-11-252-62/+0
| | | | | | | | | | This was copied from P2B-F without doing any modification. It never worked. Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Change-Id: I2c90688c8ff8c3bd272d24f059e8e1bfb86e2b4a Reviewed-on: http://review.coreboot.org/7555 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* getac/p470: Change COM3/COM4 IRQ to move it out of PCI IRQ ones.Vladimir Serbinenko2014-11-251-2/+2
| | | | | | | | | | | | | The suggested IRQs 10 and 11 would conflict with PCI IRQ assignment (10 for most interrupts on this board). Suggest IRQ 6 instead. It's actually a noop since the code is commented out. Change-Id: I0fdd8e2091d3dc79cfb1809a9ea5e1e841ca598a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7476 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* lint-stable: Ignore .bin files for whitespace check.Vladimir Serbinenko2014-11-251-1/+1
| | | | | | | | | | | | .bin is the most convenient format for storing SPDs and since it's not text format, whitespace check is useless and gives false positives. Change-Id: I8a7569eac8a1dfbffabe166a38e4dd3e895fdef1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7567 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko2014-11-2510-80/+80
| | | | | | | | | | | | | According to spec IRQ1 isn't available for PIRQ assignment. Has gone unnoticed probably because modern OS use MSI or at least APIC and even with noapic don't use IRQ1 with PCI IRQs. Change-Id: Idc7db249007df629b27e8cae41cc80358d5306f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7478 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
* northbridge/amd/agesa/family16kb: Add MMCONF res to PCI_DOMAINEdward O'Callaghan2014-11-251-22/+21
| | | | | | | | | | | | | | | This is a port of the following: commit d5c998be99709c92f200b3b08aed2ca3fee2d519 The coreboot resource allocator doesn't respect resources claimed in the APIC_CLUSTER. Move the MMCONF resource to the PCI_DOMAIN to prevent overlap with PCI devices. Change-Id: I49167dd3f15d0203a7db8950880ab03171d5c170 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7533 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* amd/fam10: Fix pstate configurationPatrick Georgi2014-11-251-1/+1
| | | | | | | | | | | | Testing for msr.hi | PS_EN_MASK doesn't make sense. Change-Id: If3305e4255f227be4bb7a5496a625ef2a50a5808 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7578 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* google/butterfly: fix off-by-one issuesPatrick Georgi2014-11-251-2/+2
| | | | | | | | | | | | GPIOs 32 and 64 used the wrong code path. Change-Id: I1d293cf38844b477cac67bc19ce5e5c92a6e93ca Found-by: Coverity Scan Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7577 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* northbridge/amd/agesa/family12/dimmSpd.c: Use ARRAY_SIZE macroEdward O'Callaghan2014-11-251-3/+2
| | | | | | | | | | Change-Id: Icf980088c196b152cc4e5e179f7b7e334b695ccc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7574 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* build system: unify linker use across gcc and clangPatrick Georgi2014-11-254-28/+10
| | | | | | | | | | Let's just call ld directly for gcc, too. Change-Id: I305eb92ed0d21b098134a7eb5a9f9fe3b126aeea Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7553 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 20:53:01 +0000