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* soc/intel/skylake: Enable LAN depending on devicetree configurationFelix Singer2020-07-2921-25/+3
| | | | | | | | | | | | | | | | | Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting. Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* soc/intel/skylake: Enable SATA depending on devicetree configurationFelix Singer2020-07-2924-36/+14
| | | | | | | | | | | | | | | Currently SATA gets enabled by the option EnableSata, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SATA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableSata setting. Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
* mb/google/zork: update stapm parameter for berknipKevin Chiu2020-07-291-3/+3
| | | | | | | | | | | | | | | | sustained_power_limit = 12w fast_ppt_limit = 24w slow_ppt_limit = 20w BUG=b:162377903 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Change-Id: I9baf9990e26edbbadfba85bc16b380c46684033d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/intel/tglrvp: Add support for USB Type-C connector device propertiesJohn Zhao2020-07-296-2/+35
| | | | | | | | | | | | | | This change updates TGLRVP configuration to have USB Type-C connector device properties filled into ACPI SSDT. TEST=Built and booted to kernel on tglrvp boards. Verified the USBC scope under LPCB.EC0.CREC with required connector device properties. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/soc/rockchip: Add missing <{stddef,stdint}.h>Elyes HAOUAS2020-07-292-0/+3
| | | | | | | | Change-Id: I0b7bdd9f46846bc9c3d9672b50dfe2fb166fcb78 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* src/acpi: Add missing <{stdbool,stdint}.h>Elyes HAOUAS2020-07-292-0/+4
| | | | | | | | Change-Id: Ic09c04cfa18408c61d7e99ea29bccc23acbd7144 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* doc/getting_started: update name of file generated by "make savedefconfig"Jonathan Zhang2020-07-291-1/+1
| | | | | | | | | | | Update kconfig.md to reflect that defconfig (instead of mini-config) file is generated by running "make savedefconfig". Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I4075e5b51e3c504eaad25e3abfc52ba593364ee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dBDuncan Laurie2020-07-291-1/+1
| | | | | | | | | | | | | | | | The HSIO tuning guide recommendation for the default USB3 settings is to have de-emphasis set to -3.5dB with the equation 20*log(X/64). 0x29 results in a value close to -3.5dB and it is the value that was used for the default on past platforms so I used it here as well. BUG=b:160721468 TEST=Ensure WWAN device does not disconnect during use. Change-Id: Ia594996cb55523dacce0d4bef98cc217321c62de Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/dedede/var/magalor: Generate SPD ID for supported partsKarthikeyan Ramasubramanian2020-07-293-0/+18
| | | | | | | | | | | | | | | | | | | Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory part being added is: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR BUG=None TEST=Build the magalor board. Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/jasperlake: Clean up report_cpu_info() functionUsha P2020-07-291-24/+4
| | | | | | | | | | | | | | | This patch uses the fill_processor_name function in order to fetch the CPU Name. TEST = Successfully able to build boot Waddledoo and verify the cpu_name from CPU log "CPU: Genuine Intel(R) CPU 0000 @ 1.10GHz". Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I532e05d9bb71fdff24e086e81ec72ffe8dc2c22d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43480 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/apcb: Strip SPD manufacturer informationRob Barnes2020-07-292-0/+13
| | | | | | | | | | | | | | Strip manufacturer information from SPDs before injecting into APCB. This allows more flexibility around changing DRAM modules in the future. BUG=b:162098961 TEST=Boot, dump memory info Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h>Elyes HAOUAS2020-07-292-0/+4
| | | | | | | | Change-Id: I34b8083eb14d5f82699cf92744000a416d2816ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib/libgcov.c: Do not redefine `alloca`Angel Pons2020-07-291-1/+1
| | | | | | | | | | | This is already defined in <commonlib/helpers.h> and it gets included implicitly by some other header. Fixes building with code coverage. Change-Id: Id2dc6cc34b6f1d351d8e1b52d8cc4ada8666c673 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/supermicro/x11-lga1151-series: correct superio interruptsMichael Niewöhner2020-07-292-6/+14
| | | | | | | | | | | | | | | | | Add interrupts for all enabled superio devices to quiet the warning about missing interrupts in devicetree. Vendor uses interrupt 0x00 for all devices except SUART* and KBC, so let's do that, too. This also changes SWC from 0x0b to 0x00. Verified with superiotool on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I7a6dc7345f020e53415a7d0d104ce93ab4b194fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonas Löffelholz Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Revise "24 hours wait period" rulesPatrick Georgi2020-07-291-9/+36
| | | | | | | | | | | | They're more or less the same but reworked for hopefully some more clarity. There have been some best practices around documenting the reason for expedited processing so let's make them official, too. Change-Id: I620e48016a1ceda2ac43f26624ed21af01f6a0a5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43484 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/ocp/tiogapass: Configure IPMI FRB2 watchdog timer via VPD variablesJohnny Lin2020-07-297-2/+67
| | | | | | | | | | | | | | | | | Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value in romstage. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Add RO_VPD and RW_VPD sections. Tested on OCP Tioga Pass. Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* acpi: Fix dptf_write_fan_perf to include Revision fieldTim Wawrzynczak2020-07-281-1/+3
| | | | | | | | | | | | | | | | When emitting a fan's _FPS (Fan Performance States) table, the revision field was missing. According to ACPI spec 6.3, the current revision is zero, so add that Package entry before the others. BUG=b:149722146 TEST=verified first element of \_SB.DPTF.TFN1._FPS is 0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If16d4751f1d924807f5087d93b348e58d5265197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43978 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/intelp2m: Add Intel Pad to Macro utilityMaxim Polyakov2020-07-2819-0/+2728
| | | | | | | | | | | | | | | | | | This patch adds a new utility for converting a pad configuration from the inteltool dump to the PAD_CFG_*() macros [1] for coreboot and GPIO config data structures for FSP/sdk2-platforms/slimbootloader [2,3]. Mirror: https://github.com/maxpoliak/pch-pads-parser.git [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] https://slimbootloader.github.io/tools/index.html#gpio-tool [3] 3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35643 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Add controls for SMT and downcoringMarshall Dawson2020-07-282-0/+11
| | | | | | | | | | | | BUG=b:159198385 TEST=confirm both using Mandolin Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I91654817608ab62e4104959b8876333911b90175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43299 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/soc/amd: Add include <types.h>Elyes HAOUAS2020-07-285-4/+5
| | | | | | | | | | BIT(x) needs <types.h>. Change-Id: Icaeda969cae52d9c62d976db4ead0e734efa838c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/zork: Add Bluetooth reset gpios to devicetreeRob Barnes2020-07-285-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add bluetooth reset gpio 143 to dalboz baseboard devicetree Add bluetooth reset gpio 14 to trembyle baseboard devicetree Remove bluetooth reset_gpio when not supported on a specific board variant. BUG=b:157580724 TEST=Boot Ezkinil with Realtek 8822CE, observe log [ 12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized [ 12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized [ 12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized [ 12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized [ 12.273700] usb 3-2: GPIO lookup for consumer reset [ 12.273702] usb 3-2: using ACPI for GPIO lookup [ 12.273705] acpi device:18: GPIO: looking up reset-gpios [ 12.273707] acpi device:18: GPIO: looking up reset-gpio [ 12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0 [ 12.273737] gpio gpiochip0: Persistence not supported for GPIO 14 [ 12.273960] usbcore: registered new interface driver btusb Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* device: Add find_dev_nested_path helper functionRob Barnes2020-07-282-0/+31
| | | | | | | | | | | | | | | Add find_dev_nested_path helper function to simplify finding deeply nested devices. BUG=b:157580724 TEST=Find bluetooth device on dalboz Change-Id: I48fa5fcad0030fb6dcea97b9fc76e1d3d3f9b28f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso: Enable VBNV_BACKUP_TO_FLASH for psp_verstageMartin Roth2020-07-281-1/+1
| | | | | | | | | | | | | | | | Enable the Kconfig flag VBOOT_VBNV_CMOS_BACKUP_TO_FLASH for psp_verstage to save the vbnv data to the SPI rom. BUG=b:161366241 TEST=Boot Morphius, Read rom from SPI and extract the RW_NVRAM region. See that it's getting updated. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0d4b92fa321a8409468b8d8fc40be0d4b57b664b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43487 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Init SPI in psp_verstageMartin Roth2020-07-281-0/+2
| | | | | | | | | | | | | | SPI needs to be initialized to save VBNV (Vboot Non-Volatile memory) to flash. BUG=b:159811539 TEST=Build & boot. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iebf3ed3f5d6be0dda717d91d5b2fbcf2a1cc43cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/43308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4John Zhao2020-07-281-1/+22
| | | | | | | | | | | | | | | | Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux. TEST=Built image-tglrvp-up4.bin successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I8423ddbb5bc189899a9e19e7da6e2ee7b7fecc18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Doc/mb/facebook/monolith: Use correct TianoCore commit hashPaul Menzel2020-07-281-1/+1
| | | | | | | | | | | The commit hash is the same as the SeaBIOS one, and is indeed from the SeaBIOS repository. Change-Id: I820b9b748778050fc694c13b1e2b2fc80885b4f1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43749 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i945/gma.c: Remove extra indentationElyes HAOUAS2020-07-281-5/+4
| | | | | | | | Change-Id: If48cd055477011cece7921cea462aab176e170fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/picasso/Makefile.inc: force an error if PSPBTLDR_FILE is not setRonald G Minnich2020-07-281-1/+1
| | | | | | | | | | | | | | | | | | Currently, if PSPBTLDR_FILE is empty, the md5sum will hang forever on stdin, leading to the appearance of a hung script. This is confusing. There's no option to md5sum to say "you must use this file", so instead, use dd with if to ensure we at least get an error if the file is not found. Not optimal, but better than what we have now. Change-Id: Ia13035bc592bdf2a515dfd2e052ae9135e218612 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/smbios: Bump to version 3.0Patrick Rudolph2020-07-282-3/+43
| | | | | | | | | | | | | | Fill in the new fields introduced with version 3.0 and install the new entry point structure identified by _SM3_. Tested on Linux 5.6 using tianocore as payload: Still able to decode the tables without errors. Change-Id: Iba7a54e9de0b315f8072e6fd2880582355132a81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/lenovo/{l520,t430}/acpi/platform.asl: Rearrange codePeter Lemenkov2020-07-282-14/+27
| | | | | | | | | | | Rearrange code to unify with the rest of xx20/xx30 boards. No functional changes - just smaller diff output. Change-Id: I5867b2a90b2e53a3a9dd919701f1e185cb39cf78 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/lenovo/*/acpi/superio.asl: Replace with GPLv2+ equivalentPeter Lemenkov2020-07-2814-3/+25
| | | | | | | | | | | | | | | Replace functionally identical files with t440p/acpi/superio.asl which is licensed under more flexible terms (GPL-2.0-only or no licensing terms vs. GPL-2.0-or-later). Apart from licensing terms these files are identical. This makes diff between boards smaller. Change-Id: I1cd4a85b65ceaa0a383416e7276ad41a41783cb7 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43685 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intelvbttool: Fix some typos in error messagesPeter Lemenkov2020-07-281-3/+3
| | | | | | | | Change-Id: Id6298883c39c21179b13696dab630818b81026ff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43905 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/madoo: Generate SPD ID for supported partsDtrain Hsu2020-07-283-0/+12
| | | | | | | | | | | | | | | | | | | Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR BUG=b:161215903 BRANCH=NONE TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib61af2399541c4caf4a310a34e778e0ba1cbd3ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/43802 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/madoo: Add audio support (ALC5682, MX98360A)Dtrain Hsu2020-07-281-7/+20
| | | | | | | | | | | | | | Select the drivers for ALC5682 codec and MX98360A spk amp BUG=b:161407664 BRANCH=NONE TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibe3d878b1058bfae4143d96be854884e61394ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/madoo: Configure USB port setting for MadooDtrain Hsu2020-07-281-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow schematic to modify USB port setting and clean up I2C clock tuning. USB2 [0]: USB Type C Port 0 USB2 [1]: USB Type C Port 1 USB2 [2]: None USB2 [3]: USB Type A Port 1 USB2 [4]: None USB2 [5]: Camera USB2 [6]: None USB2 [7]: WLAN module - BlueTooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: USB Type C Port 1 (Sub/B side) USB3 [2]: None USB3 [3]: USB Type A Port 1 USB3 [4]: None USB3 [5]: None BUG=b:161407664 BRANCH=NONE TEST=Build the coreboot image on madoo board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ia73593f52adee3806e725127891f084a08bf1360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43750 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/madoo: Configure GPIO for MadooDtrain Hsu2020-07-282-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | Follow schematic to modify some GPIO pins. GPP_D12 - NC Pin GPP_D13 - NC Pin GPP_D14 - NC Pin GPP_D15 - NC Pin GPP_E0 - NC Pin GPP_E2 - NC Pin GPP_H6 - NC Pin GPP_H7 - NC Pin GPP_S02 - NC Pin GPP_S03 - NC Pin BUG=b:161407664 BRANCH=NONE TEST=Build the coreboot image on madoo board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I85aadfb0d020055eec921c7646c16ae6c95a606f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43745 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/var/voxel: Add memory configurationSheng-Liang Pan2020-07-282-0/+62
| | | | | | | | | | | | | | Update dq/dqs mappings based on voxel schematics. BUG=b:155062561 BRANCH=none TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ida248094a1477fe457026e18f313385082ee71f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/var/volteer: I2C5 trackpad bus freq 400 kHz Johnny Li2020-07-281-0/+43
| | | | | | | | | | | | | | | The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If59502aec7c3ab55864a518d626cde52aee18373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43746 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/i2c/max98373: fix error message formattingCaveh Jalali2020-07-281-1/+1
| | | | | | | | | | | | | This adds a missing newline to a printk in the max98373 driver. BUG=none TEST=verified BIOS boot log is properly formatted on volteer. Change-Id: I1c989729bdc71736975901566023e0057a6d0556 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* PCI IDs: Add PCI ID for the realtek 5261Caveh Jalali2020-07-281-0/+1
| | | | | | | | | | | | | | This adds the PCI ID of the realtek 5261 PCIe to SD Express card reader. BUG=b:161774205 TEST=none Change-Id: I4d5e6cfca59b02adc74a0c148281a92421fe209d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer2: Add support for passive USB-C daughterboardCaveh Jalali2020-07-281-1/+14
| | | | | | | | | | | | | | | | This copies over the USB daughterboard device tree config from volteer to volteer2. These two boards are basically identical in this area so the config should also be identical. BUG=b:158673460 TEST=none Change-Id: If8a82bc18b36d92a1c851b49612edfbefa18ec54 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* libpayload: Replace include/compiler.h with commonlib/bsd's versionPatrick Georgi2020-07-281-17/+27
| | | | | | | | | | This ensures that it's available under BSD license terms. Change-Id: Ica13014b847473fee02516be0b27684c6cfb07bc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/wifi: Adapt generic wifi driver into a chip driverKarthikeyan Ramasubramanian2020-07-287-23/+50
| | | | | | | | | | | | | | | | Re-organize the existing generic wifi driver into a generic wifi chip driver. This allows generic wifi chip information to be added to the devicetree. BUG=None TEST=./util/abuild/abuild Change-Id: I63f957a008ecf4a6a810c2a135ed62ea81a79fe0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43768 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/waddledee: Add discrete WiFi configurationKarthikeyan Ramasubramanian2020-07-281-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:161734657 TEST=Ensure that the discrete WiFi information is built into ACPI table. Scope (\_SB.PCI0.RP01) { Device (WF00) { Name (_UID, 0x923ACF1C) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x43, 0x03 }) } } Change-Id: I9a9259e167fc213291b89e151729553ec4649eaf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43769 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/cavium: Fix up license headersAngel Pons2020-07-285-5/+0
| | | | | | | | | | Drop a leading blank line in the license header comment. Change-Id: Ic3d7568303f9d816a8727a2960270e7667d41104 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* nb/intel/haswell: Enable DMI ASPMAngel Pons2020-07-282-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | On Haswell platforms, the processor and the PCH are two separate dies, and communicate through a high-speed bus. This is DMI (Direct Media Interface) on traditional two-package platforms, but single-package Haswell LP variants use OPI (On-Package Interconnect) instead. Since OPI is not routed through the mainboard, most link parameters are static and cannot be changed. OPI self-initializes on boot, anyway. However, DMI needs to be initialized in firmware. On Haswell, the MRC initializes the physical DMI link, but things like topology and power management need to be configured as well. And we don't do that properly. We enable ASPM on the PCH side of the DMI link, but not on the SA side. Both sides need to use the same settings, so enable DMI ASPM on the SA. Clearing the error status bits needs to be done on all Haswell variants. Tested on Asrock B85M Pro4, still boots. Change-Id: Ie97ff56eec9f928cfd2d5d43a287f3e0d2fbf3cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* src: Never set ISA Enable on PCI bridgesAngel Pons2020-07-289-14/+6
| | | | | | | | | | | | | | | | | | | | | Looks like no one really knows what this bit would be useful for, nor when it would need to be set. Especially if coreboot is setting it even on PCI *Express* bridges. Digging through git history, nearly all instances of setting it on PCIe bridges comes from i82801gx, for which no reason was given as to why this would be needed. The other instances in Intel code seem to have been, unsurprisingly, copy-pasted. Drop all uses of this definition and rename it to avoid confusion. The negation in the name could trick people into setting this bit again. Tested on Asrock B85M Pro4, no visible difference. Change-Id: Ifaff29561769c111fb7897e95dbea842faec5df4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/intel/braswell/fadt.c: Use `ACPI_ADDRESS_SPACE_IO` macroAngel Pons2020-07-281-5/+5
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: Ie53a61c0ebb71bd7f2f9e931c175f35c3646ac6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43930 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI S3: Clean up resume pathKyösti Mälkki2020-07-283-9/+6
| | | | | | | | | | | | | | | | | | Remove the obscure path in source code, where ACPI S3 resume was prohibited and acpi_resume() would return and continue to BS_WRITE_TABLES. The condition when ACPI S3 would be prohibited needs to be checked early in romstage already. For the time being, there has been little interest to have CMOS option to disable ACPI S3 resume feature. Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/amd/mandolin: remove ACPI_FADT_RESET_REGISTER from fadt_flagsFelix Held2020-07-281-1/+0
| | | | | | | | | | | This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does to the devicetree settings of amd/mandolin. Change-Id: I6cc0a2b60b13a809016225caf3c89f730deb4ce0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 21:05:04 +0000