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* sb/intel/i82870: Use ioapic utility functionsKyösti Mälkki2021-06-161-21/+4
| | | | | | | | | Change-Id: I60ce17fd7640fab064a3d62d8d2b3703993c7b59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55309 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/ioapic: Drop irq_on_fsb as a configurable itemKyösti Mälkki2021-06-1618-73/+13
| | | | | | | | | | | | | | | | | | | | | | | APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/Kconfig: fix CONSOLE_UART_BASE_ADDRESS for SoC UART2Felix Held2021-06-161-1/+1
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6deb2a4c632d39112dcce71f076742a1b62ee89b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/zork: enable UART0 in devicetreeFelix Held2021-06-162-0/+2
| | | | | | | | | | | | | | This a mainly a preparation for adding the MMIO UART devices to the chipset devicetree. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso: introduce and use devicetree aliases for I2C2&I2C3Felix Held2021-06-1613-12/+15
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/common/block/acpi/bert: fix NULL checkFelix Held2021-06-161-1/+1
| | | | | | | | | | | | | | | In acpi_soc_get_bert_region after the bert_errors_region call is was checked if the region parameter is NULL after the call; since region is a parameter of acpi_soc_get_bert_region, it's non-NULL. What we should be checking here is if region points to a non-NULL pointer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Coverity (CID:1457506) Change-Id: I0523504d65725ab2d2df4db28a5dedd90697b917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/cezanne/include/soc/iomap: add eMMC MMIO base addressesFelix Held2021-06-161-0/+3
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie97bd6ad076f0ce35fc997d954a003a1252184e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne,picasso/include/soc/iomap: reflow I2C_DEVICE_COUNTFelix Held2021-06-162-4/+2
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7edae2142120dec9e11ef823b561401b7e0bc208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne/acpi/mmio: use AOAC offset definesFelix Held2021-06-161-6/+7
| | | | | | | | | | | | Even though the code is currently commented out, replace the magic numbers with the existing defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0dbbadf71f2e5a4d23ee998e2aa0a8b67205845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne: factor out AOAC offset definesFelix Held2021-06-164-14/+23
| | | | | | | | | | | | Factoring out those defines allows using them easily in the ACPI code without having to use preprocessor macros. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9dfddb0d4f32a542fa652ff8c14e932c224f247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso/acpi/sb_fch: use AOAC offset definesFelix Held2021-06-161-6/+7
| | | | | | | | | | | Replace the magic numbers with the existing defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d98ea8c5bb0e487c7eef0b0a1cdada9cb04df4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso: factor out AOAC offset definesFelix Held2021-06-164-13/+21
| | | | | | | | | | | | Factoring out those defines allows using them easily in the ACPI code without having to use preprocessor macros. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99cb03de8782a0eeeb505f567b982099b0e8a18d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controllerFelix Held2021-06-162-0/+2
| | | | | | | | | | | BUG=b:184978118 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I03554a151aa6a6d9e15d74c63cd02239b788808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* sb/intel/lynxpoint: Update xHCI _PS0 and _PS3 methodsAngel Pons2021-06-161-0/+20
| | | | | | | | | | | Lynx Point PCH ACPI reference code version 1.9.1 has two additional magic steps, which were already present in Broadwell. Add them. Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* MRC platforms: Fix MRC version printk format specifiersAngel Pons2021-06-163-3/+3
| | | | | | | | | | The printed values are unsigned, and should be printed accordingly. Change-Id: Ie5edce914c389c70460b1ed3390731e3568340dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/broadwell: Drop `config_t` typedefAngel Pons2021-06-162-5/+3
| | | | | | | | | | | | The typedef needlessly hides the actual type of the variables. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I58a58cd402ec679960f460e80b37ff2afb8e3974 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/intel/haswell: Select `HAVE_DISPLAY_MTRRS`Angel Pons2021-06-162-1/+1
| | | | | | | | | | This option is valid for Broadwell as well as Haswell. Change-Id: I4f1e9663806bae279f6aca36f09a0c989c12e507 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/broadwell: Separate PCH KconfigAngel Pons2021-06-162-68/+72
| | | | | | | | | | | | | | Split up PCH Kconfig into a separate file. While we're at it, also sort selected options alphabetically. Tested with BUILD_TIMELESS=1, coreboot.rom for the Purism Librem 13 v1 remains identical when not adding the .config file in it. Change-Id: Ic3ff982e7108bf2d25a22e56ac2fbb93070df164 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb/intel/lynxpoint/Kconfig: Fix typo in help textAngel Pons2021-06-161-1/+1
| | | | | | | | | | Lynxpont ---> LynxPoint Change-Id: I5af67079ead389beeafd9172aa1b98980dacbd38 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/prodrive/hermes: Use serial numbers from BMCAngel Pons2021-06-163-1/+34
| | | | | | | | | | | The BMC EEPROM layout has been updated to contain system and mainboard serial numbers. Use these values in SMBIOS Type 1 and Type 2 tables. Change-Id: I55b51a856b4ad28fd56b02015b2e1d49cd629735 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55275 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/broadwell: Drop unused PSS macrosAngel Pons2021-06-161-6/+0
| | | | | | | | | | | | | These macros were used to generate ACPI P-state entries, but Broadwell now uses Haswell CPU code. These macros are unused and can be removed. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ib2baca2964d9177e7ab6630d4ced22c5d332fb6e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/broadwell/pch: Use equivalent Lynx Point ASLAngel Pons2021-06-164-54/+5
| | | | | | | | | | | | | Keep deduplicating code. Have Broadwell PCH ASL borrow some equivalent Lynx Point ASL files, and drop the now-unused files from Broadwell PCH. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: If5a8712a846bbf7c42db92167763935dee74c26f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* broadwell boards: Use Haswell hostbridge.aslAngel Pons2021-06-165-204/+4
| | | | | | | | | | | | | Use hostbridge.asl from Haswell instead of Broadwell. Both files are equivalent. Then, drop the now-unused hostbridge.asl from Broadwell. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/broadwell: Use Haswell memmap.h in iomap.hAngel Pons2021-06-161-17/+1
| | | | | | | | | | | | | | Include Haswell memmap.h from Broadwell iomap.h to deduplicate identical definitions. This also prevents the definitions from falling out of sync while the unification process is ongoing. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I850e5521effba3818f4e2a13b94281bf07857d50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/broadwell: Include `pci_irqs.asl` from PCHAngel Pons2021-06-163-3/+3
| | | | | | | | | | | Move the inclusion of `pci_irqs.asl` into PCH scope in order to allow deduplicating northbridge ACPI code. Change-Id: I541913226b26662f3798ae9c25ab1ac33cf2ed45 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/broadwell: Add missing resources in ASLAngel Pons2021-06-161-0/+3
| | | | | | | | | | | Taken from Haswell code. These resources also exist on Broadwell and should be reported to the OS. Change-Id: I45f2a6a9140d72c1cc2ee8b72621dc16c815b621 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/haswell: Fully handle GDXCBAR and EDRAMBARAngel Pons2021-06-163-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | GDXCBAR and EDRAMBAR are accounted for when reporting resources to the allocator, but they are not present in the DSDT. In addition, coreboot does not enable either range, but MRC.bin sets up GDXCBAR and does not disable it afterwards. Not reporting GDXCBAR in the DSDT can result in resource conflicts, and not enabling EDRAMBAR can cause issues on CPUs with eDRAM. Enable both GDXCBAR and EDRAMBAR in coreboot code, and report these ranges in the DSDT. This matches what Broadwell does. The value for the `GDXC_BASE_ADDRESS` macro matches what MRC.bin programs as well. Tested on Asrock B85M Pro4 with an i7-4770S (no eDRAM): - Still boots - EDRAMBAR is now enabled with base address of 0xfed80000 - GDXCBAR is still mapped with base address of 0xfed84000 Change-Id: I5538873b30e3d02053e4ba125528d32453ef6572 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/haswell/memmap.h: Define MMIO window sizesAngel Pons2021-06-163-10/+20
| | | | | | | | | | | | | Add defines for the sizes of northbridge MMIO windows and use them where applicable. The macro names have been taken from Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I845cba8acbd478cd325d2e364138336d985f9c34 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/intel/haswell: Enable MCA loggingAngel Pons2021-06-161-0/+6
| | | | | | | | | | | | Intel document 493770 (Haswell BIOS Writer's Guide) revision 1.8.0 recommends writing all ones to the IA32_MCi_CTL registers in order to enable all MCA error reporting. Change-Id: Ib5d2c759483026b5b4804c5a4b2b969d2269af22 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55463 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/asus/p8x7x-series: Add P8H77-V as a variant of P8X7X seriesBill XIE2021-06-1614-0/+576
| | | | | | | | | | Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ic811e24bd72da84e5ca8f5b09f2eb65872153b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55111 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* security/tpm/tspi: Reduce scope of tspi_init_crtmArthur Heymans2021-06-162-19/+17
| | | | | | | | | | | | This is only called locally. Change-Id: Ie3eaf659a2868eee1d4688885495c413f94f42e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* soc/mediatek/mt8195: Add ddp driver to support eDP outputjason-jh.lin2021-06-163-0/+553
| | | | | | | | | | | | | | | Add ddp (display controller) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings on mt8195 to support multi-layer display. BUG=b:189985956 Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Change-Id: I9d5dd1025c4766218c2b1d86b9b1f97f2eab53d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55509 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/denverton_ns: Remove SOC specific FSP location overridesArthur Heymans2021-06-162-26/+2
| | | | | | | | | | | | | | | | | | 1) FSP-S should not run XIP 2) Overriding the FSP-T location conflicts with the location set in drivers/intel/fsp2_0 This fixes a regression caused by commit 0f068a600e (drivers/intel/fsp2_0: Fix the FSP-T position) Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/G6WRFITANOS2JEYG3GKB2ZNVCLUZ6W7P/ Change-Id: I381781c1de7c6dad32d66b295c927419dea7d8be Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/intelp2m/fsp: Update some deprecated macrosBenjamin Doron2021-06-161-4/+4
| | | | | | | | | | | | | | | | Avoid using deprecated macros, where possible. "GpioResetPwrGood" represents multiple valid updated values, depending on the GPIO community and will be more difficult to update. While Kabylake supports both sets of macros, it will cause build errors on Coffeelake. In the GPD group, replace with "GpioDswReset." Replace with "GpioResumeReset" in any GPP group. Change-Id: Iab0bb09adad997bef3a2133c443471d4c634f423 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
* nb/intel/haswell: Update some "Misc ICH" commentsAngel Pons2021-06-161-2/+2
| | | | | | | | | | | | One of the Memory32Fixed entries covers the TXT private and public spaces, and another covers the TPM registers. Update the comments. Change-Id: I261d74c113fabf1d152964efd8c91de85eba4179 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix themArthur Heymans2021-06-162-20/+10
| | | | | | | | | | | | | | | Move locking CPU MSRs during CPU init instead of using CONFIG_PARALLEL_MP_AP_WORK functions. The AES Lock enable bit caused CPU exception errors as this should not run on HT siblings. The set_aesni_lock() function takes care of that. Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55098 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik2021-06-165-58/+67
| | | | | | | | | | | | | | | | Disable all display related UPDs if IGD is not enabled as FSP don't need to perform display port initialization while IGD itself is disabled else assign UPDs based on devicetree config. TEST=Dump FSP-M display related UPDs with IGD enable and disable to ensure patch integrity. Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-163-59/+25
| | | | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on ADL. Change-Id: I92671992ec14fd2adca1635b0791ac8b456332e9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55292 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Make use of is_devfn_enabled()Subrata Banik2021-06-163-17/+8
| | | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on EHL. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iadf9145a11f27ff0e182f146b6fe5a01e6cf3ed8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/tigerlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-163-53/+22
| | | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on TGLRVP. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ic9d91b711bab83de1911e0b7ea876f2ad018c937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55330 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/jasperlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-163-24/+11
| | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on dedede Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I4919a1ec02df50bc41fd66d5f3a352108a7aa04c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/cannonlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-162-52/+18
| | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on CML. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib5df5fd32e2e2742d349754a942bf81ca505dd39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/apollolake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-163-11/+5
| | | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on Reef. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I900038dd4b2e2d89b1236bbd26bec5f34483b9f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/mp_init: Support both xapic and x2apic with common codeArthur Heymans2021-06-161-30/+10
| | | | | | | | | | | | | | | | | Trigger mode LAPIC_INT_LEVELTRIG was only used with LAPIC_DM_INIT, specifically for (obsolete) Init Level De-assert. Level LAPIC_INT_ASSERT is required to be set for all other delivery modes other than LAPIC_DM_INIT. This reverts the two above changes that X2APIC mode support introduced to the IPI for LAPIC_DM_SMI. Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tpm/tss: Remove local variablePatrick Georgi2021-06-151-2/+1
| | | | | | | | | | | | | | | | | Depending on how the "middle-end" (yes, the gcc developers are serious about that) optimizer ends up mangling the code, there may or may not be a complaint about x being used uninitialized when it's clearly not used at all. So instead, why keep x in the first place? memcpy(foo, NULL, 0) is the same as memcpy(foo, some_uninitialized_variable, 0) in that it does nothing. Change-Id: Ib0a97c3e3fd1a2a6aff37da63376373c88ac595d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vc/mediatek/mt8195: Match definition with declarationPatrick Georgi2021-06-151-1/+1
| | | | | | | | | | gcc 11 insists. Change-Id: Icec68ab7a3c0bce9b18e37c1b6f41603c97181e2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vc/mediatek/mt8195: Fix code indentationPatrick Georgi2021-06-151-2/+2
| | | | | | | | | | | | gcc 11 complains about it otherwise. Change-Id: Ic9b2124506f33c76902d3b44481f14182c1d74b9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* 3rdparty/libhwbase: Update to latest ToTPatrick Georgi2021-06-151-0/+0
| | | | | | | | | | This update adds a commit to fix building libgfxinit with gcc 11 Change-Id: I5c0e3823ab7219667f9430bce74e4f2fba0c0c3a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src/console/init.c: Make get_log_level static inline againJakub Czapiga2021-06-153-15/+19
| | | | | | | | | | | | | CB:55356 removed static inline declarations from get_log_level(). This commit puts them back. It also changes the method of accessing static symbols in tests/console/routing-test to source file inclusion like in CB:46458 to avoid changing tested source file. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iaa5dcbccb327f819374967be51ef642b1fb25e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55473 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/w541: Add ThinkPad W541Amersel2021-06-1518-0/+728
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the ThinkPad W541 based on Peter Lemenkov's initial W541 port. Compiled and tested with SeaBIOS and Tianocore booting into Arch Linux 5.10.32-lts. The Haswell mrc.bin blob is required. Tested working: - SATA SSD - SATA DVD drive - M.2 SATA - All USB ports - SD card reader - Speakers/headphone jack - Keyboard/touchpad - libgfxinit - VGA - mini DisplayPort (Thunderbolt untested) - eDP laptop screen - NVIDIA GPU in Linux - Camera/Mic - Smartcard reader - Internal flashing when IFD is unlocked - ThinkPad basic dock (VGA, USB, Ethernet) - CMOS options - WLAN - Bluetooth - Ethernet - Using me_cleaner - All DDR3 slots Not working: - Keyboard backlight - First boot can take up to 20s (MRC.bin is slow) Untested: - Thunderbolt - Internal flashing when IFD is locked - Other ThinkPad docks (DisplayPort, DVI, Audio) - ExpressCard slot - Battery thresholds - WWAN card - Fingerprint reader - USB Debug console Signed-off-by: Justin Wu <amersel@runbox.me> Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52659 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 03:11:42 +0000