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* {acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer2022-12-2732-88/+88
| | | | | | | | | | Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/acpi: Replace constant "One" with actual numberFelix Singer2022-12-2749-146/+146
| | | | | | | | | Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* {superio,ec}/acpi: Replace constant "One" with actual numberFelix Singer2022-12-2737-154/+154
| | | | | | | | | Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/marasov: Add DmaProperty for ISHSubrata Banik2022-12-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | On Marasov, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on Marasov. TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* drivers/intel/ish: Add ADL-P ISH DIDSubrata Banik2022-12-272-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ISH ID for ADL-P to ensure dynamic ASL code is added into SSDT. With this patch: Scope (\_SB.PCI0.ISHB) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/marasov: Remove ISH firmware-nameSubrata Banik2022-12-271-4/+0
| | | | | | | | | | | | | | | | | | For marasov, the ISH main firmware will be included in the CSE region in flash instead of loading it from rootfs. So remove the ISH firmware-name. TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not loaded by kernel, and device still goes to S0i3. Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com>
* sio/winbond/w83627hf/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxElyes Haouas2022-12-261-8/+16
| | | | | | | | | | | | Replace Divide (a,b,c,d) with: c = a % b d = a / b Change-Id: I0e9fdabbb4b5bd9698968cd8acb497dcde14e433 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71508 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxFelix Singer2022-12-262-4/+10
| | | | | | | | | | | | | | Replace `Divide (a, b, c, d)` with these instructions: c = a % b d = a / b Change-Id: I44366be5b5145a5d19f85df7a2f338866cb9c8b0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/lenovo/s230u/acpi: Replace Not(a, b) with ASL 2.0 syntaxFelix Singer2022-12-261-2/+2
| | | | | | | | | | Replace `Not (a, b)` with `b = ~a`. Change-Id: I0f18119c8e91222e59a56b8509f12c6ece6d04ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71514 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/acpi: Replace Not(a) with ASL 2.0 syntaxFelix Singer2022-12-264-4/+4
| | | | | | | | | | Replace `Not (a)` with `~a`. Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pc80/vga: Add NULL check for `vga_line_write()`Subrata Banik2022-12-261-0/+3
| | | | | | | | | | | | | This patch ensures vga_line_write() returns if the argument 1 (aka output string) is NULL. TEST=Able to build and boot Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I716ce82c0afe21f7fe2f6d7bdc5229f8087242fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* sio/acpi/pnp.asl: Replace Not(a) with ASL 2.0 syntaxElyes Haouas2022-12-261-1/+1
| | | | | | | | Change-Id: Icbd2ab736b9fc3300ee82896c31b373fe92e1d54 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71509 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/ironlake/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas2022-12-261-1/+1
| | | | | | | | Change-Id: I6af7131e151700569d50e8bc42bfaeb7a58fa7d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71507 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas2022-12-261-1/+1
| | | | | | | | Change-Id: I75bc048d9e04be8d0cab25f6aad1c71d3e7a4008 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71506 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/haswell/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas2022-12-261-1/+1
| | | | | | | | Change-Id: I1ff0132e17b08f492828eb13d66e167eae45250d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71505 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/baytrail/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas2022-12-263-5/+4
| | | | | | | | Change-Id: Iab611cda1083da4378a6e509d11ea26bdbb45edd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71503 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/braswell/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas2022-12-262-3/+2
| | | | | | | | | Change-Id: I7da6ee3c5bce6b32874e59ad46290b86db8f97c6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71502 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Make use of is_devfn_enabled() functionDinesh Gehlot2022-12-251-3/+2
| | | | | | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on MTL. Port of 'commit 50134eccbdf4 ("soc/intel/alderlake: Make use of is_devfn_enabled() function")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I54bbd2bdba69a19e0559738035916fa7ac60faaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel: Move max speed API to commonDinesh Gehlot2022-12-255-21/+7
| | | | | | | | | | | | | | | | | | | | | | This patch moves API "smbios_cpu_get_max_speed_mhz()" to common code from board specific. This API was made generic in 'commit d34364bdea12 ("soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macro")' BUG=NONE TEST=Boot and verified that SMBIOS max speed value is correct on brya and rex. (brya) dmidecode -t : "Max Speed: 4400 MHz" (rex) dmidecode -t : "Max Speed: 3400 MHz" Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I87040ab23319097287e191d7fc9579f16d716e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/riscv: Use 'enum cb_err'Elyes Haouas2022-12-251-7/+7
| | | | | | | | | Change-Id: I5a589a43b1e92cca6b531ca161174eefb5592569 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* arch/x86: Use 'enum cb_err'Elyes Haouas2022-12-254-19/+20
| | | | | | | | | Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/docker: Update setuptools to get dtc buildingMartin Roth2022-12-251-1/+2
| | | | | | | | | | | | | | | | | python3-setuptools installed via apt-get is not currently working to build dtc from git.kernel.org. Falling back to setuptools version 58.2.0 allows it to build again. The failure message was: /usr/lib/python3/dist-packages/setuptools/installer.py:27: SetuptoolsDeprecationWarning: setuptools.installer is deprecated. Requirements should be satisfied by a PEP 517 installer. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I04cb6d776c3748f9a4b0cfc4ffd4f46458560d3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71500 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/mb/google: Add support for rexSubrata Banik2022-12-246-0/+39
| | | | | | | | | | Add the file templates for creating a new variant of Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4abca1f999accc008eb2549fcc13199b8d9bdc7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex: Enable DPTF functionality for Rexzhaojohn2022-12-243-0/+10
| | | | | | | | | | | | | | Enable DPTF functionality for Meteor Lake Rex board. BUG=b:262498724 TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board. Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATETracy Wu2022-12-241-2/+1
| | | | | | | | | | | | | | | | | | | With enabling FSP Notify Phase APIs, it has chance to issue a global reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY ), which CSE already in idle mode and cause failure. For this reason we should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select SOC_INTEL_CSE_SEND_EOP_LATE instead. BUG=b:261544011 BRANCH=firmware-brya-14505.B TEST=tested and verified on Marasov, make sure this kind of global reset can be executed successfully. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/volteer/eldrid: Correct DDR4 SPDs for EldridJohnny Li2022-12-243-3/+3
| | | | | | | | | | | | | | | | | | Correct DDR4 SPDs from H5AG36EXNDX019 to H5AG36EXNDX017. DRAM Part Name ID to assign H5AG36EXNDX017 0 (0000) BUG=b:236739240 BRANCH=Volteer TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If248714088835eb5dd48fa12223c273199297228 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71160 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spd/ddr4: Correct Hynix ddr4 part number from H5AG36EXNDX019 to H5AG36EXNDX017Johnny Li2022-12-242-2/+2
| | | | | | | | | | | | | | | Correct Hynix ddr4 part number H5AG36EXNDX019 to H5AG36EXNDX017 by Hynix Memory spec. BUG=b:236739240 BRANCH=Volteer TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I6195fa1402691afc303f5223de48f552660cd97f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71159 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/zydron: Use SSFC for mipi instead of fw_configDavid Wu2022-12-243-8/+23
| | | | | | | | | | | | | | Kano didn't use SSFC in mass production, however Zydron needs SSFC for 2rd source mipi instead of fw_config. BUG=b:262939431 TEST=Boot to OS and check functional with ov2740/hi556 camera. Change-Id: Idb2a35d67af0b5a7dedc66b0f7eccd8a3b4612d1 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
* soc/amd/mendocino: Split the EFS from the AMDFW bodyKarthikeyan Ramasubramanian2022-12-242-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Contents of unsigned AMDFW in RW sections are verified twice in PSP verstage - first time by vboot verifying the firmware body, second time by CBFS verification while the file is loaded to update PSP about the boot region. This redundant verification adds to boot time. Minimize the redundancy by splitting the EFS header from the AMDFW body and keep them as 2 separate CBFS files. This helps to improve the boot time by another 25 ms. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe boot time improvement of ~25ms. Before: 6:end of verified boot 363,676 (16) 11:start of bootblock 641,392 (277,716) After: 6:end of verified boot 361,655 (16) 11:start of bootblock 616,967 (255,312) Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Write EFS and AMDFW body in separate filesKarthikeyan Ramasubramanian2022-12-241-13/+119
| | | | | | | | | | | | | | | | | Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Use GPP_C15 as WWAN_DPR_SAR_ODLSubrata Banik2022-12-241-2/+2
| | | | | | | | | | | | | BUG=b:263413949 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I453fe8e1f4b4b8d4730ade259899d76aec949a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex: Rename GPP_D07 to FPMCU_UWB_MUX_SELSubrata Banik2022-12-241-2/+2
| | | | | | | | | | | | | BUG=b:263412235 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia444cc8e3666fe15479ece81d068f9e8f1d339ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/71228 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/nissa/var/craask: Use get_wifi_sar_fw_config_filenameEric Lai2022-12-241-10/+1
| | | | | | | | | | | | Use get_wifi_sar_fw_config_filename to remove the duplicate code. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I04176fee373e534d42c72506df73a092ad55e65b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/volteer/var/lindar: Use get_wifi_sar_fw_config_filenameEric Lai2022-12-241-6/+1
| | | | | | | | | | | | | | Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34e6b4f435880d62936ae54f19ba2ec752eced2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/var/taeko: Use get_wifi_sar_fw_config_filenameEric Lai2022-12-241-5/+1
| | | | | | | | | | | | | | Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7a764d8cc3160c26abad9c1757812b955bef066 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/nissa/var/pujjo: Use get_wifi_sar_fw_config_filenameEric Lai2022-12-241-17/+1
| | | | | | | | | | | | Use get_wifi_sar_fw_config_filename to remove the duplicate code. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ifde714c19f7ab9fe08f870060037db190a80dbd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* vc/google/chromeos: use fw_config field to return sar filenameEric Lai2022-12-242-0/+21
| | | | | | | | | | | | | | Use fw_config field to return sar filename instead of fw_config probe. Return filename unconditionly because the sar_id must be valid in CBI. If invalid sar_id, the file won't exist in CBFS by design. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* lib: add stub for fw_config_get_fieldEric Lai2022-12-241-0/+6
| | | | | | | | | | | | Return UNDEFINED_FW_CONFIG with disabled fw_config. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0d31ff3ba7706039c622bd1ec825d216a0f21fe4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* Revert "security/tpm/: turn tis_{init,open} into tis_probe"Sergii Dmytruk2022-12-2311-101/+157
| | | | | | | | | | | | | | | This reverts commit d43154486d27323f64334203e9bc8baf08af6845. From CB:68991: This causes CraterLake boot up process to die. Investigation in progress. Change-Id: I4a6c11b0e638a891108fe230bdaea92d5fbca020 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: siemens-bot Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Revert "drivers/pc80/tpm: probe for TPM family of a device"Sergii Dmytruk2022-12-231-78/+24
| | | | | | | | | | | | | This reverts commit 907a81e2a79f394c316644429165ae66679bafd6. This reportedly breaks TPM and measured boot flow completely. Change-Id: Id0d98ecc7807faa1617ad16dc9a24343c5a66b06 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/poppy: Use runtime detection for touchscreens/digitizersMatt DeVillier2022-12-236-11/+13
| | | | | | | | | | | | | | | | | | Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens/digitizers. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on all poppy variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I4c1d8ae8c41c1f4283718a86fccbf5ae4fc399b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/poppy: Set touchpad/touchscreen IRQs to LEVEL vs EDGEMatt DeVillier2022-12-234-6/+6
| | | | | | | | | | | | | | The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: Iee01dac943b6c2955f7af42ce0e9395fc609682f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70920 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/poppy: Implement touchscreen,digitizer power sequencingMatt DeVillier2022-12-237-18/+75
| | | | | | | | | | | | | | | | For touchscreens/digitizers on poppy variants, drive the enable GPIO high and hold in reset in romstage, then release from reset in ramstage. This will allow coreboot to detect the presence of i2c touchscreens/digitizers during ACPI SSDT generation (enabled in a subsequent commit). TEST=tested with the rest of patch train Change-Id: I90ac4f09c343a28328f7d30254f0448cbe0c78b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/siemens/mc_apl{4,7}: Limit I2C bus speed to 100 kHz on bus 7Werner Zeh2022-12-234-0/+35
| | | | | | | | | | | | | | | | | | Due to a high I2C bus load on the mainboard I2C frequency of 400 kHz leads to poor signaling. Therefore limit the I2C speed to 100 kHz for this bus. In addition, add a generic I2C device with 100 kHz bus speed to the devicetree so that the OS will not switch to higher clock rates, too. Test= Measure the I2C signals at coreboot and OS runtime and ensure the clock is always at 100 kHz. Change-Id: I6b0a642cd3f5b77331663ac8c76ed0a116ae77ca Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71227 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl7: Init I2C controller before PTN3460 is initializedWerner Zeh2022-12-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | When PTN3460_EARLY_INIT is selected, the PTN3460 (DP-2-LVDS-bridge) will be initialized before all devices are initialized. This is necessary to get a valid EDID data set into the PTN3460 before the graphic controller is initialized in order to be able to show a splash screen. For ptn3460_init() to work properly the I2C bus this bridge is connected to needs to be initialized. As this I2C bus initialization would be done too late in the normal flow, it needs to be called here explicitly before ptn3460_init() to initialize the I2C bus with the needed conditions. Otherwise the default I2C settings of the controller will be used which results in a clock rate too high for this mainboard. Test=Measure I2C bus signals and make sure that the clock is <= 400 kHz. Change-Id: I1775fb7c2d29f765224d0e7c7ff9fcd4dbf847c5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86: Set up a separate stack for APsArthur Heymans2022-12-233-7/+14
| | | | | | | | | | | | | | APs use a lot less stack, so set up a separate stack for those in .bss. Now that CPU_INFO_V2 is the only code path that is used, there is no need to align stacks in c_start.S. Change-Id: I7a681a2e3003da0400843daa5d6d6180d952abf5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/intel/cmn/block/pmc: Add pmc_or_mmio32 utility functionTim Chu2022-12-232-0/+13
| | | | | | | | | Change-Id: I5f9845dd3ea098d990710eaaa2d5db495f876cdd Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/broadwell: Add Kconfig option to hide Intel MEMatt DeVillier2022-12-232-1/+12
| | | | | | | | | | | | | | | On broadwell devices, coreboot currently disables and hides the ME PCI interface by default, without any way to opt out of this behavior. Add a Kconfig option to allow for leaving the ME PCI interface enabled, but set the default to disabled as to leave the current behavior unchanged. Change-Id: If670d548c46834740f4e21bb2361b537807c32bf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* sb/intel/lynxpoint: Add Kconfig option to hide Intel MEMatt DeVillier2022-12-232-1/+12
| | | | | | | | | | | | | | | On lynxpoint devices, coreboot currently disables and hides the ME PCI interface by default, without any way to opt out of this behavior. Add a Kconfig option to allow for leaving the ME PCI interface enabled, but set the default to disabled as to leave the current behavior unchanged. Change-Id: I994cb5b05829eddad2e423a7440a9458f9952370 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/meteorlake: Add DPTF ACPI Device IDs into header fileSubrata Banik2022-12-231-0/+20
| | | | | | | | | | | | | | This patch adds DPTF ACPI Device IDs into the header file (soc/dptf.h). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib78258ac1b9a5252bb5e6fae4d7cc30a3f103e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71126 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-03 22:34:25 +0000