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* soc/braswell: Add CPUID for D0 steppingDivya Sasidharan2016-01-141-0/+1
| | | | | | | | | | | | | Original-Reviewed-on: https://chromium-review.googlesource.com/309122 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12727 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* ec/: add missing license headersMartin Roth2016-01-142-4/+40
| | | | | | | | | | | | | | | thermal.asl was written as part of the coreboot project, so gets the standard coreboot license header. ec_commands.h came from the chrome ec tree, so gets the BSD license from that tree as mentioned in the header that has been replaced. Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* acpi/: add missing license headerMartin Roth2016-01-141-0/+13
| | | | | | | | | | | These were mostly written as part of the coreboot project, so get the standard coreboot license header. Change-Id: Ief13339647d3172e65bb18e6dcb54312a5c9472e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12917 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* arch/x86/include: add missing license headersMartin Roth2016-01-1412-0/+156
| | | | | | | | | | | These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12912 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* soc/braswell: Fix P-state tableSubrata Banik2016-01-144-6/+33
| | | | | | | | | | | | | Incorrect bus-core-ratio been used to generate P-state table Original-Reviewed-on: https://chromium-review.googlesource.com/290681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12731 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* intel/skylake/pcr.c: error out on invalid size in pcr read/writeMartin Roth2016-01-141-2/+2
| | | | | | | | | | | | The read and write routines take a number of bytes to write, which should be 1,2, or 4. We now return an error if an invalid size is specified. Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12936 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* xcompile: More updates on ARM64 Erratum flagsMartin Roth2016-01-141-4/+5
| | | | | | | | | | | | | | | | | | | I tried to handle the checking for the config flag internal to xcompile, but the config flags don't appear to have been loaded into the environment by make at that point. This does update the if to check if the flag is even set before putting anything into .xcompile though. If the LDFLAG isn't set, there's no point in appending anything. Also removes the LP version of the erratum config flag, which was a copy/paste mistake from $(CONFIG_LP_COMPILER_GCC). Change-Id: I3d8b0328c85310393a120741a498bc18867a6f54 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* mb/lenovo/x200: Add panel power sequence valuesNico Huber2016-01-141-0/+5
| | | | | | | | | | | | Values are taken from the vendor BIOS of my X200s. Notable effect: Stops display from flashing during native graphics init / Linux mode setting. Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* nb/intel/gm45: Backport configuration of panel power timingsNico Huber2016-01-142-9/+54
| | | | | | | | | | | Register settings are the same as on newer chips (compare sandy- bridge), just at different locations. Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* nb/intel/gm45: Drop unnecessary panel power handlingNico Huber2016-01-141-15/+0
| | | | | | | | | | | | | | Skip everything but the final setting of PP_CONTROL, i.e. triggering the power up. The settings with PANEL_UNLOCK_REGS are useless as no lockable registers were touched in between. Also the loop waiting for the panel power up to finish was a no-op as the registers with the power timings were never filled (see follow-up commits). Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbfstool: Change FMAP granularity to 16 bytesStefan Reinauer2016-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Instead of looking for an FMAP at every byte, only search down to a granularity of 16 bytes, reducing the time for a cbfstool call by 0.3s when no FMAP is found. Signed-off-by: Stefan Reinauner <reinauer@chromium.org> BUG=none BRANCH=none TEST=time ./cbfstool coreboot.rom add -f locale_de.bin -n locale_de.bin -t 0x50 -c lzma is 0.3s faster than before. Change-Id: Icb4937330e920ae09928ceda7c1af6a3c5130ac7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc92d838ba9db7733870ea6e8423fa4fa41bf8fe Original-Change-Id: Idbaec58a199df93bdc10e883c56675b419ab5b8e Original-Reviewed-on: https://chromium-review.googlesource.com/317321 Original-Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/12932 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* cbgfx: add error code to cbgfx_initDaisuke Nojiri2016-01-142-3/+9
| | | | | | | | | | | | | | | | | | | | cbgfx_init can fail for multiple reasons. These codes help debugging cbgfx_init. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: Ifaa8d91b058bd838a53faf5d803c0337cb1e082c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4caf2496f3583e133f3f216ec401515c267e6e7b Original-Change-Id: I84f60dd961db47fa426442172ab19676253b9495 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315550 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12930 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile: Add 3rdparty to CPPFLAGS_commonJimmy Huang2016-01-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | In some occasions, Coreboot may need to include the header file from 3rdparty directory. By adding 3rdparty directory to Coreboot include path, we can include 3rdparty header file directly. BRANCH=none BUG=none TEST=build pass Change-Id: I8ed68bd330eae1211736a91b213c5dc0af2f7fa9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d6a86b3488ebbc9d8f5f46e922106b71034e7127 Original-Change-Id: Ib8e9f059f88a8c6767f872af8760e91186ae5ec3 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315021 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12929 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* cbfstool: fix address truncated problemHC Yen2016-01-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | In parse_elf_to_stage(), it uses 32-bit variable to handle address. The correct address type is Elf64_Addr. Use uint64_t to prevent address to be truncated. BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I1abcd16899a69b18dd10e9678e767b0564b2846e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ebc1aae0ae4ca30802a80a4a4e2ae0c0dad4d88a Original-Change-Id: I21f8057ddf13e442f1cf55da6702c3449ba0cc35 Original-Reviewed-on: https://chromium-review.googlesource.com/292553 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12927 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* mainboard/lenovo: reserve century byteAlexander Couzens2016-01-1412-29/+43
| | | | | | | | | | | | | The century byte is used by most RTC (default 0x32@nvram). Even the century byte can disabled via ACPI it's more safe to reserve it's space. Because some RTC will act with that byte anyhow. Some OS overwrite it when syncronize the RTC. Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/11853 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* cbfstool: reorder help textPatrick Georgi2016-01-141-1/+1
| | | | | | | | | | | | hashcbfs was spliced in a line early, mixing up 'extract' and 'cbfshash' help texts. Change-Id: I86d4edb9eec0685a290b2dd4c2dc45d3611eba9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12922 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* arch/arm64: add missing license headersMartin Roth2016-01-135-0/+65
| | | | | | | | | | | These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* arch/arm: add missing license headersMartin Roth2016-01-138-0/+104
| | | | | | | | | | | These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I74438e8032c84f4190ef49f306969f7157234001 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* utils: Remove old license text from help & disclaimer fileMartin Roth2016-01-137-22/+5
| | | | | | | | | | | | The license text that we decided to remove was removed from the headers of these files, but was still left in the help text. Remove it from those locations as well. Change-Id: I0e1b3b79f1afa35e632c4a4dd09a8bf2b02eaa6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* tree: drop last paragraph of GPL copyright header from new filesMartin Roth2016-01-13122-488/+0
| | | | | | | | | | | This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in KconfigMartin Roth2016-01-133-0/+3
| | | | | | | | | | | | | | Because these platforms haven't been getting build testing, they've missed out on some of the improvements that the other platforms have gotten. Enable MAINBOARD_HAS_LPC_TPM so that they will build. Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12865 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* intel/northbridge/sandy: raminit code cleanupPatrick Rudolph2016-01-131-1/+0
| | | | | | | | | | Remove redundant call to dram_mrscommands(). Change-Id: I157915b4432093c556b538433e3337db1e9c525f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* [WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUMENico Huber2016-01-131-0/+1
| | | | | | | | | Change-Id: Ifa7dd593f70921a99d937104960e26100de28089 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12421 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* northbridge/intel/x4x: clean up includesMartin Roth2016-01-136-10/+14
| | | | | | | | | | | | | | | - Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h - Move TPMBASE and TPM32() definitions into iomap.h - Use "" style include for x4x.h in nortbridge files. - Move includes of .h files out of x4x.h and into the c files that need them. - Protect function definitions in bootblock. Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbfstool: Remove duplicate code lineWerner Zeh2016-01-131-1/+0
| | | | | | | | | | | Remove duplicate line which sets baseaddress parameter. Change-Id: Idfbb0297e413344be892fa1ecc676a64d20352bf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12904 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* util/lint: Add lint script to run kconfig_lintMartin Roth2016-01-121-0/+18
| | | | | | | | | | | | The lint target in the makefile relies there being a script using this particular naming format, so add a shell script front end to run the kconfig linter. Change-Id: I029c1cd3bbf3837c9f1d86c391ae5cabfa53685d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12903 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* util/lint/kconfig_lint: Run through perltidy to fix whitespaceMartin Roth2016-01-121-70/+93
| | | | | | | | Change-Id: I7f04156fff0b65ea262b12961ce76ef329d358ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12902 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* lint: rename lint-006-checkpatch because board name is lint-006Martin Roth2016-01-121-0/+0
| | | | | | | | | | Checkpatch should be 007. Change-Id: Ib71c50ad1a63a3a743391cd8fea9f79cd08ef6f3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12901 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Makefile: Add toolchain version checkMartin Roth2016-01-122-0/+24
| | | | | | | | | | | | | | | This is an initial check for the coreboot toolchain versions. It currently checks binutils, gcc, clang, and iasl. The other components are slightly more difficult to test, but should follow on shortly. If the toolchain is not the correct version, make will halt with an error. Change-Id: I41daf6c4545c01dc21231d78fd081bbcf77c4726 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12846 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
* amd/cimx/sb800/pci_devs.h: Update guard #define nameMartin Roth2016-01-121-2/+2
| | | | | | | | | Change-Id: Ieae41cab97293831a0c49c3b472b9e6c62ba36c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12899 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* intel/skylake: Remove check for Microcode loaded by MEMartin Roth2016-01-121-22/+1
| | | | | | | | | | | | This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* google/guado: initial upstream migrationMatt DeVillier2016-01-1230-0/+2243
| | | | | | | | | | | | | | | Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream, using google/auron and google/panther as refs. TEST=built and booted guado with full functionality Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12800 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* Makefile: Correct spelling in help messageWerner Zeh2016-01-121-1/+1
| | | | | | | | | | | Correct wrong spelled "subnit" in help message. Change-Id: Iadbf483835ee4c1b6e3faa454d1cae2660b99c5e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` styleNico Huber2016-01-121-76/+77
| | | | | | | | Change-Id: Ifae3822b6c28832f6aa05a4ffd8f02067a923f2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12883 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* autoport: Add missing castsVladimir Serbinenko2016-01-111-2/+2
| | | | | | | | Change-Id: I04abdd48f5e2440756f9b03041d46c773f200368 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/12890 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* fsp1_1: Remove #if protection in header - It's not neededMartin Roth2016-01-101-4/+0
| | | | | | | | | | | | | There's nothing in these files that needs to be hidden if GOP support is disabled. Removing this allows skylake to build when GOP support is turned off. Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12859 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* lenovo/x220: Enable USB 3 controllerMarian Tietz2016-01-102-2/+4
| | | | | | | | | | | | | | | | | | Since only X220 with i7 have the USB3 controller this was probably overlooked. Before this patch lspci on Linux would not show the NEC USB 3 controller as well as the PCI bridge it is behind. After, both the bridge and the NEC controller can be found in the output: 05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: Marian Tietz <mtcoreboot@gmail.com> Reviewed-on: https://review.coreboot.org/12882 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* buildgcc: Print out all missing tools then haltMartin Roth2016-01-091-1/+7
| | | | | | | | | | | | Instead of printing out a single tool that needs to be installed each time buildgcc is run, print out the entire list of tools to be installed, then halt. Change-Id: I7761760eef3c45ba371f882a4f987408945bb3e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12856 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltageMartin Roth2016-01-081-0/+2
| | | | | | | | | | | | | | | | | I think this has a fairly low likelyhood of happening, but if AGESA can't determine the voltage of the memory, it assignes a value of 255 to the variable that it later uses to read from an 3-value array. There is an assert, but that doesn't halt AGESA, so it would use some random value. If the voltage can't be determined, fall back to 1.5v as the default value. Fixes coverity warning 1294803 - Out-of-bounds read Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12855 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* fsp_baytrail: Add additional PCI space above 4GBMartin Roth2016-01-081-0/+15
| | | | | | | | | | | | | | | | | | This just tells the OS that it can use the 16GB of address space at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit physical address space. This could be hardcoded into the UMEM definition, but doing it this way makes it more plain what it's doing, and allows for modification to put it just above the top of upper memory, similar to what is done with the standard PCI region above the top of low memory. Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12791 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>
* intel/braswell: Disable IFD & ME by default so abuild can buildMartin Roth2016-01-071-2/+2
| | | | | | | | | | | The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so disable them by default for now. Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* mainboard: Drop abuild.disabled files for Braswell boardsStefan Reinauer2016-01-072-4/+0
| | | | | | | | | | | Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* buildgcc: Don't request that optional tools be installedMartin Roth2016-01-071-3/+7
| | | | | | | | | | | | | | | Previously, when we tested for g++ and two different versions of clang, if the earlier versions were not found, buildgcc would still request that they be installed. This obviously isn't needed, and isn't the desired outcome. Now, if one of the first tests fails, nothing gets printed. If all the tests fail, it tells you to install either g++ or clang. Change-Id: I71359f59c4c6bee3c3c55e4e6105f11e6ca51527 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12852 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Correct some common spelling mistakesMartin Roth2016-01-0729-58/+58
| | | | | | | | | | | | | | | | - occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* src/vendorcode/amd: correct spelling of MTRRPaul Menzel2016-01-0740-69/+69
| | | | | | | | Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/4806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* f14: Increase AP stack to 8k on 64bitStefan Reinauer2016-01-071-0/+4
| | | | | | | | | | | | This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/11025 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
* google/cyan, intel/strago Kconfig: Only ask to display SPD onceMartin Roth2016-01-072-11/+0
| | | | | | | | Change-Id: Ic3df9bf7d7f3c4c39789f3f496bcb7fc2ee50931 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* xcompile: Quote variables to prevent globbing and splitting.Martin Roth2016-01-071-7/+7
| | | | | | | | | | | | | | | Quoting variables prevents word splitting and glob expansion, and prevents the script from breaking when input contains spaces, line feeds, glob characters and such. See shellcheck warning SC2086 Change-Id: Ib6ca46b64a621c4bea5c33ac312f2824b0386235 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12845 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* xcompile: Use local variables in the test functionsMartin Roth2016-01-071-3/+5
| | | | | | | | | | | | | | Using the local variables instead of positional parameters helps readability. - Add and use the local variables in testcc. - Use the existing local variables in testld. Change-Id: Ice13288b830a7aa043b360eaee8e36f060589a18 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12844 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* xcompile: use $() instead of backticksMartin Roth2016-01-071-6/+6
| | | | | | | | | | | | While the backtick syntax isn't actually deprecated, the $() syntax is preferred. Since both styles were being used in this script, settle on the new standard for all cases. Change-Id: I33770d666781b4fa34c909411e0d220c2540dbb4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-27 02:13:59 +0000