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* soc/intel/alderlake: Enable eMMC based on dev enabledKrishna Prasad Bhat2022-02-214-0/+28
| | | | | | | | | | | | | 1. Add eMMC device function in pci_devs.h. 2. Enable eMMC device and configuration based on dev enabled. 3. Add SOC acpi name for eMMC. Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake NKrishna Prasad Bhat2022-02-212-0/+81
| | | | | | | | | | | Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it. Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* src/acpi: Add macro for FADT Minor Version and use itElyes Haouas2022-02-217-13/+28
| | | | | | | | Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
* libpayload/cbfs: Add missing new line at the end of error messagesJakub Czapiga2022-02-211-2/+2
| | | | | | | | Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ieec281e4f1c67e40976892b3dd1780d2f3802df4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Documentation/contributing/gsoc: Use paths to md filesFelix Singer2022-02-211-7/+7
| | | | | | | | | | | Replace HTTP links with paths to Markdown files where possible. Change-Id: I0ecca6460105b10b81c4fc014f00235b5d9b861c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* Documentation/contributing/gsoc: Fix formattingFelix Singer2022-02-211-4/+4
| | | | | | | | | | | Fix formatting when text should be bold. Change-Id: I7a88ddc0a56dba8c05d0997f37121d0f2cc84ce6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* crossgcc: Upgrade CMake to 3.22.2 versionElyes HAOUAS2022-02-213-2/+2
| | | | | | | | Change-Id: I4272f72dd6ed686dbad5615a0ab44c8c632b5930 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Documentation/contributing: Add GSoC info siteFelix Singer2022-02-202-0/+250
| | | | | | | | | | | Add a site containing general information for GSoC contributors and mentors. It was initially copied from https://www.coreboot.org/GSoC. Change-Id: I5c21d026118cba571dc6b817e89cc4da296a1799 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* mb/amd/chausie: increase RW_MRC_CACHE size in FMAPFelix Held2022-02-192-2/+2
| | | | | | | | | | | | | | On Sabrina SoCs the size of the APOB has increased, so the size of the RW_MRC_CACHE FMAP sections needs to be increased in order for the data to still fit in the corresponding FMAP partition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: remove the delay from for WWAN _ON method.Cliff Huang2022-02-181-1/+0
| | | | | | | | | | | | | | | | Remove unecessary delay in RTD3 _ON Method after PERST# dessartion. TEST: 2022-02-10T18:22:53.204391Z INFO kernel: [ 0.190287] ACPI: Power Resource [RTD3] (on) 2022-02-10T18:22:53.204395Z INFO kernel: [ 0.194252] ACPI: Power Resource [RTD3] (off) Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I9bc36af6e6c944fcd3de23b7d49640ad9d25642d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* nb/amd/pi/00730F01/northbridge.c: Use 'pci_{and,or}_config'Elyes Haouas2022-02-181-10/+4
| | | | | | | | Change-Id: Ifd77c90fe82e20df91562fccea8b5d89dd4a193d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* soc/intel/apollolake: Create alias for GEN_PMCON1 as GEN_PMCON_ASubrata Banik2022-02-181-0/+1
| | | | | | | | | | | | This patch creates alias for GEN_PMCON_A to maintain parity with other IA SoC PMC register definitions. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id9a23c58a325cb544c50cbda432fe3117eea22fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/denverton_ns: Add function to clear PMCON status bitsSubrata Banik2022-02-185-21/+43
| | | | | | | | | | | | | | | | | | | | | | | This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579. Additionally, removed `PMC_` prefix from PMC configuration register macros GEN_PMCON_A/B and ETR3. Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on function numbers. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/alderlake: Skip FSP Notify APIsSubrata Banik2022-02-182-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alder Lake SoC deselects Kconfigs as below: - USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE to skip FSP notify APIs (Ready to boot and End of Firmware) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. Additionally, created a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again config. TODO: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects required configs. BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0198c9568de0e74053775682a44324405746389a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/common/cse: Add `finalize` operation for CSESubrata Banik2022-02-181-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects all required configs: BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik2022-02-1816-78/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brya/redrix{4es}: Disable unused USB2/TCSS portsWisley Chen2022-02-182-0/+10
| | | | | | | | | | | | | Disable unused USB2/TCSS Ports. BUG=b:217238553 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* arch/x86/acpi: Add code for KEY_MENUBoris Mittelberg2022-02-183-0/+3
| | | | | | | | | | | | | | | | Support of MENU key (aka hamburger) for Chromebooks with Vivaldi keyboard BUG=b:215038215 TEST=manually tested on Anahera device: pressing T13 key opens menu Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835 Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Update ec_commands.hBoris Mittelberg2022-02-181-12/+64
| | | | | | | | | | | | This change copies ec_commands.h directly from the Chromium OS EC repo, with the exception of changing the copyright header to SPDX format. Update to commit hash af9a119 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I1f2a140257d6127fb19bb514bc345466247b7499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* MAINTAINERS: Add myselfFred Reitberger2022-02-181-0/+5
| | | | | | | | Change-Id: I441369bc47ad4758c2188cb4e0f7e971607f72d5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/psp/Makefile: add fmap_config.h dependencyFelix Held2022-02-181-1/+5
| | | | | | | | | | | Compiling efs_fmap_check.c depends on fmap_config.h already being generated, so add this dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAPFelix Held2022-02-182-3/+7
| | | | | | | | | | | Also add the Makefile dependency on the fmap_config.h file to make sure that this file already exists when it's included. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* include/acpi/acpi.h: Drop non-existing update_ssdt()Elyes Haouas2022-02-181-2/+0
| | | | | | | | Change-Id: Ie8535d97e883d3fed9414fb5ba65a0797b989c0d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* include/acpi/acpi.h: Drop non-existing update_ssdtx()Elyes Haouas2022-02-181-1/+0
| | | | | | | | Change-Id: I2fd8470ed2b8e8f00de4ba64258aac1db52744c1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/brya/var/{redrix, redrix4es}: Use ACPI _PLD macroSubrata Banik2022-02-182-72/+12
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/felwinter: Update DPTF parameters for FelwinterJohn Su2022-02-181-13/+10
| | | | | | | | | | | | | | | | | Follow thermal team design to remove TSR3 sensor and update thermal table for next build. The DPTF parameters were verified by thermal team. BUG=b:219690502 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya/var/vell: Correct MIPI camera infoShon Wang2022-02-181-1/+1
| | | | | | | | | | | | | The CIO2 port was incorrectly set to 2, while the correct port is 1 BUG=b:210801553 TEST=Build and boot on vell, camera works correctly now Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/volmar: Use ACPI _PLD macroSubrata Banik2022-02-181-6/+12
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e0b51ee4db73bdff79365d4954a3245a430f140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62051 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/vell: Use ACPI _PLD macroSubrata Banik2022-02-181-8/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e4837489d90c2edd7deaa2af0533085f1ff5ae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62049 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/taniks: Use ACPI _PLD macroSubrata Banik2022-02-181-8/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id44213c7dd4d0df97a6c57d7f1b9d950baaf0e1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62047 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/{taeko, taeko4es}: Use ACPI _PLD macroSubrata Banik2022-02-182-73/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61830 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/{primus, primus4es}: Use ACPI _PLD macroSubrata Banik2022-02-182-96/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61828 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/kano: Use ACPI _PLD macroSubrata Banik2022-02-181-36/+6
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I07cef3b619991afb6337c38a631ee159677d30a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61826 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/{gimble, gimble4es}: Use ACPI _PLD macroSubrata Banik2022-02-182-72/+12
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0274f03926d97fc543b98f3fb961580283202806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61825 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/felwinter: Use ACPI _PLD macroSubrata Banik2022-02-181-36/+6
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I33e4501fd689d642682891c7f5bc9cb7ca5e331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61824 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/{brya0, brya4es}: Use ACPI _PLD macroSubrata Banik2022-02-182-96/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1940246fd88db29054f85c43672adc97dc90fa04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61823 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/{anahera, anahera4es}: Use ACPI _PLD macroSubrata Banik2022-02-182-96/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d8a8a7e2b1e490726986139014cdfcf1271c64b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61805 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: Use ACPI _PLD macroSubrata Banik2022-02-181-8/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idb8f30b2d1069aea1d5ce7c5dda7f99de33a7c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61803 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi: Use ACPI macros to configure USB port _PLD objectSubrata Banik2022-02-181-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds two ACPI macros for USB port A and C _PLD object configuration as: 1. ACPI_PLD_TYPE_A 2. ACPI_PLD_TYPE_C The configurable parameters are - Panel, Port is exposed on which face of a panel. - Horizontal, Horizontal position on the panel where the device connection point resides. - Group - Token, Unique numerical value identifying a group. - Position, Identifies this device connection point’s position in the group (i.e. 1st, 2nd). BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I245b17019b6d3c5e380c16cb3c9f4edc4dd10cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya/var/volmar: Fix PLD group orderSubrata Banik2022-02-181-2/+2
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iddf0727a538f2063cfabbec1f900c488331f33c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/vell: Fix PLD group orderSubrata Banik2022-02-181-2/+2
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/taniks: Fix PLD group orderSubrata Banik2022-02-181-4/+4
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia9bc235c257abce2a3cd63cfd1b17ac356267d8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/taeko4es: Fix PLD group orderSubrata Banik2022-02-181-2/+2
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic3fbf307bfa42bd377c8f23c1837a6d15cb378e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/{redrix, redrix4es}: Fix PLD group orderSubrata Banik2022-02-182-8/+8
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I80d9038d1f41d65201d6bfdb808708f997d71faf Reviewed-on: https://review.coreboot.org/c/coreboot/+/62031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/{primus, primus4es}: Fix PLD group orderSubrata Banik2022-02-182-4/+4
| | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic97d48633ef1f246c181046ec32ab81614ba5ceb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya/var/kano: Fix PLD group orderSubrata Banik2022-02-181-2/+2
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I78734f685672347b06783f834643347a35c59e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/{gimble, gimble4es}: Fix PLD group orderSubrata Banik2022-02-182-4/+4
| | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4e051b21ca55d25c6fc6cfb529078b18adaab2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62028 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/{anahera, anahera4es}: Fix PLD group orderSubrata Banik2022-02-182-16/+16
| | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0c72a5c5306d63c5fce24bf727704d212d0ad0f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya/var/agah: Fix PLD group orderSubrata Banik2022-02-181-7/+7
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9cef57bbaf3e3519b7f6a7e3d86979722b598ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/guybrush: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSPJan Dabros2022-02-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Guybrush platforms have I2C3 controller which is shared between PSP and X86. In order to enable cooperation, PSP acts as an arbitrator. Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is binded on the OS side. With this change in place it is important to use correct kernel version which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3 available and thus TPM device available in OS, what may end up as a serious error - guybrush refuses to boot without access to TPM. BUG=b:204508404 BRANCH=guybrush TEST=Build proper kernel and firmware. Run on guybrush and verify TPM functionality. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 16:24:39 +0000