summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* configs: Jenkins buildtest for FSP_CARPraveen Hodagatta Pranesh2019-12-021-0/+9
| | | | | | | | Change-Id: I004fc02bd84b7b8d5c5fb96451e59f143f0fe6d3 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/cannonlake: Fix compilationPraveen Hodagatta Pranesh2019-12-021-2/+2
| | | | | | | | | | | | | | Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h. TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP. Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/variants/helios: DPTF solution updateKane Chen2019-12-021-14/+8
| | | | | | | | | | | | | | Modify DPTF parameters. BUG=b:131272830 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I93930525edf4c5efb6b73bdfc8f16950754f7c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37272 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASEMaulik V Vaghela2019-12-021-1/+1
| | | | | | | | | | | | | | | | since we support JSL and TGL soc under tigerlake folder, we need to make sure all soc related files get compiled based on CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake. We can control soc specific file compilation through Kconfig of individual soc. Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
* superio/aspeed: Remove unused aspeed include pathMartin Roth2019-12-021-2/+0
| | | | | | | | | | | | | | | | | | | Working on some other code, I noticed that superio/aspeed was added as an include path even though I wasn't using it. I investigated and found that NOTHING is using it. The files in the aspeed directory all reference files in their own directory. The supermicro x11-lga1151-series boards are the only ones using this SIO. TEST=util/abuild/abuild -t supermicro/x11-lga1151-series Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I377066451a50452c17c9bfaa0f815f69e039984e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/glados: restore device-specific VBTsMatt DeVillier2019-12-027-3/+2
| | | | | | | | | | | | | | | | | | When migrating glados (and variants) to FSP 2.0, the older board- specific VBTs were dropped in favor of the default FSP 2.0 VBT due to compatibility issues. Now that libgfxinit is available and the default, restore the board-specific VBTs so that external displays function properly. Select MAINBOARD_NO_FSP_GOP for all variants except glados since FSP/GOP init will not function properly with the older VBTs. Test: build/boot chell and caroline variants w/libgfxinit, verify external displays now work again. Change-Id: If55a67e0d3d78e4acf80cee1733ad8e14b8847d4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/rammus: add libgfxinit supportMatt DeVillier2019-12-024-0/+40
| | | | | | | | | | | | Add libgfxinit support for rammus. Use panel init values from VBT. Test: build/boot rammus with libgfxinit and Tianocore payload Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/poppy: add VBTs for remaining variantsMatt DeVillier2019-12-025-1/+1
| | | | | | | | | | | | | Add VBT files for Atlas, Nocturne, Rammus, and Soraka variants. Extracted from ChromeOS recovery images for the respective boards. Select INTEL_GMA_HAVE_VBT for all variants except Poppy, since it doesn't have a VBT (or a recovery image from which to extract one). Change-Id: Icba2741e0b7309c22c027f956cd20cec78f34052 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/mb/intel/coffeelake_rvp: Rename COMETLAKE_RVP to COMETLAKE_RVPUGaggery Tsai2019-12-023-7/+7
| | | | | | | | | | | | | This patch renames COMETLAKE_RVP to COMETLAKE_RVPU to avoid confusion. TEST=build an image with COMETLAKE_RVPU Change-Id: I93d7b5cc0be475926bb92503b66797dc67e607f5 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36793 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/soc/intel: Add Cometlake-S and CMP-H skusGaggery Tsai2019-12-026-7/+48
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2, 8+2) P0: A0651h CML-S (6+2, 10+2) Q0/P1: A0654h CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/: Remove g_ prefixes and _g suffixes from variablesPatrick Georgi2019-12-0217-299/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* drivers/usb/ehci_debug: Add x86_64 supportPatrick Rudolph2019-12-023-4/+5
| | | | | | | | | | | | Use proper int to pointer conversions. Tested on Lenovo T410 with x86_64 enabled. Still works. Change-Id: I4ed62297fb47d7d83d4b28e80f3770de99ce70f7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37393 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/cbmem_console: Rename cbmem_console_p to current_consolePatrick Georgi2019-12-011-22/+17
| | | | | | | | | | | That way, current_console_set() also isn't necessary anymore and symmetry is re-established. Change-Id: I392ed509f490d63b0c016a80fd7ab3ef98ba8019 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* src/superio: Remove unused include <stdlib.h>Elyes HAOUAS2019-12-012-2/+0
| | | | | | | | Change-Id: I941c3d80d6b822b12a2d0c279415ab0c6b7f375b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* superio/nct5539d: include the missing acpi.h and ssdt.hMaxim Polyakov2019-12-011-1/+4
| | | | | | | | Change-Id: Idd80fae1c39f3c7c4bc66a42e9023fb7a727b024 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/x4x: Factor out hiding PCI devs in pure fnArthur Heymans2019-12-011-34/+19
| | | | | | | | | | | | | | This increases readability. Also change the update expression. '--variable' does not make much sense there. Change-Id: I64db2460115f5fb35ca197b83440f8ee47470761 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lib/imd_cbmem: Remove indirection through cbmem_get_imd()Patrick Georgi2019-11-301-8/+4
| | | | | | | | | | | It always returns the same pointer so why not use the pointer directly? Change-Id: Ib5a13edc7f3ab05c3baf9956ab67031507bdddc1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37360 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/pgtblgen: Fix typoPatrick Rudolph2019-11-301-1/+1
| | | | | | | | | Change-Id: I638eda3040c7225aa4a8b492c8dc78b0e2effba1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37369 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* kill CAR_GLOBAL_MIGRATION leftoversArthur Heymans2019-11-304-12/+2
| | | | | | | | | | Change-Id: Ia3b2c10af63cd0cab42dc39f479cb69bc4df9124 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37055 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/car.ld: Drop CAR_GLOBAL regionArthur Heymans2019-11-301-14/+1
| | | | | | | | | | Change-Id: Id66fd0528987fb3e464d400cf9ccac98752fb8f5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37327 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/*/*/early_variables.h: drop unused filesArthur Heymans2019-11-307-287/+0
| | | | | | | | | | | Kill off NO_GLOBAL_MIGRATION finally! Change-Id: Ieb7d9f5590b3a7dd1fd5c0ce2e51337332434dbd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37054 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/cache.h: Use ENV_CACHE_AS_RAM macroArthur Heymans2019-11-303-16/+2
| | | | | | | | Change-Id: Ic7b088a04165bb24b9ebcebc1580a96ce0fdfcc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/spi/flashconsole.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-301-43/+31
| | | | | | | | | Change-Id: I81a610a6d119745f2fc637629b8ba7ade76503bc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lib/cbmem_console.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-301-27/+16
| | | | | | | | Change-Id: I5c970a07c7114bff81f0048cac8eafaec35a2386 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37035 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/tsc: Remove indirection when accessing mono_timer_gPatrick Georgi2019-11-301-14/+7
| | | | | | | | | Change-Id: Ice1426cec8f9c5d9644836b0cf025be50e932f48 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/drivers: Fix two issues discovered by checkpatchPatrick Georgi2019-11-302-2/+2
| | | | | | | | | | Change-Id: I46e318333e68b999b2889f51fa2fbf140a27a54e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* AGESA,binaryPI: Add compatibility wrapper for romstage entryKyösti Mälkki2019-11-304-26/+30
| | | | | | | | | | | | This simplifies transition and reviews towards C environment bootblock by allowing single cache_as_ram.S file to be used. Change-Id: I231972982e5ca6d0c08437693edf926b0eaf9ee1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37352 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* AGESA,binaryPI: Fix stack location on entry to romstageMichał Żygowski2019-11-303-12/+27
| | | | | | | | | | | | | For BSP CPU, set up stack location to match the symbol from car.ld. For AP CPUs the stack is located outside _car_region and is currently not accounted for in the linker scripts. Change-Id: I0ec84ae4e73ecca5034f799cdc2a5c1056ad8b74 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* AGESA,binaryPI: Remove __x86_64__ long mode in CARMichał Żygowski2019-11-301-45/+0
| | | | | | | | | | Change-Id: I83a8b2325b751feeb046ce74fabd37aeb27c28dc Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37350 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* AGESA,binaryPI: Remove redundant SSE enableMichał Żygowski2019-11-301-10/+0
| | | | | | | | | | Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37349 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* AGESA,binaryPI: Remove BIST reporting in romstageKyösti Mälkki2019-11-301-11/+4
| | | | | | | | | | | | | | | For easier C environment bootblock transition by using already existing prototypes, BIST will not be passed to romstage. It is expected that bootblock will have equivalent code. Change-Id: I0f8e3657ac79277cd77c397d1b3e931e33a6f5db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37348 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* AGESA,binaryPI: Split romstage_main() to BSP and AP partsKyösti Mälkki2019-11-302-4/+32
| | | | | | | | | | | | BSP and AP have two distinct execution paths for romstage. Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* binaryPI boards: Remove BIST reportingKyösti Mälkki2019-11-306-25/+4
| | | | | | | | | | | | Can be restored with C environment bootblock. Change-Id: I077d7bf088a0ffc65e9ec0d0b1c239194dc4f4ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37347 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* binaryPI: Clean leftover romstage prototypeKyösti Mälkki2019-11-307-14/+7
| | | | | | | | | Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* AGESA,binaryPI: Flag boards with ROMCC_BOOTBLOCKKyösti Mälkki2019-11-3033-2/+31
| | | | | | | | | | | | Allows boards to be transformed to C env bootblock one at a time. Change-Id: I1cc1910a8bfb6b3495593979cbf7194b0d82c8e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37345 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* crossgcc: Upgrade acpica to version 20191018Elyes HAOUAS2019-11-294-2/+2
| | | | | | | | | | | Changes: https://acpica.org/node/174 Change-Id: I72e44429f96c2ec82092c87aea46c3ff80755d4c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* {northbridge,soc,southbridge}: Don't use both of _ADR and _HIDElyes HAOUAS2019-11-299-25/+9
| | | | | | | | | | | ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/baytrail: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-298-160/+98
| | | | | | | | | | This moves programming BAR's and setting up console in the bootblock. Change-Id: I062461cb7bfba2c4df4c20707ecda32f9857b164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36873 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/common/fsb.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-19/+12
| | | | | | | Change-Id: I151090c8d7f670f121dc7e4cbebfd720034fde33 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/imd_cbmem.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-33/+2
| | | | | | | | Change-Id: Id409f9abf33c851b6d08903bc111a6b8ec6bf8cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37032 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/spi/boot_device_rw_nommap.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-28/+12
| | | | | | | | | Change-Id: I613c28a2d06f5f0216deb75960ab660941ef8057 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37044 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/braswell: Don't reinitialize SPI after lockdownArthur Heymans2019-11-292-23/+0
| | | | | | | | | | | With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: I9fae28185470f4d25ef1818627eb76ac38cf100b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36006 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/braswell: Use sb/intel/common/spi.cArthur Heymans2019-11-294-594/+1
| | | | | | | | | | This common implementation is compatible. Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* drivers/elog/elog.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-84/+43
| | | | | | | | | Change-Id: I7dcc8d08b40560f105c22454bda1282afaa617da Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37046 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/*_stage_cache.c: drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-292-14/+7
| | | | | | | | | Change-Id: I23d5367150649a64ec6d95601f38940dbb5972f8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37034 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/amd/agesa/def_callouts.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-1/+0
| | | | | | | | | | | Drop stale comment. Change-Id: Ie9f5271074ac4876f08fa8470dbc35daf5b694b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37053 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/storage/pci_sdhci.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-7/+6
| | | | | | | | | Change-Id: Idfbc0cf24000c361c9272fe0f61797de999c9277 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37052 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/lapic/apic_timer.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-12/+8
| | | | | | | | | Change-Id: Ideac1a04d6bb1a5e9cc601be7bbfcebe56b4a5da Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37050 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/tsc/delay_tsc.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-3/+2
| | | | | | | | | Change-Id: I0a1e9fcea54444a84cc0a6ac30fe7d053261bb1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37049 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/exception.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans2019-11-291-10/+7
| | | | | | | | | Change-Id: I9e0d62d45e5b11a0c2f0867633cde2378f305ec8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37048 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 11:07:39 +0000