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* src/include: Add space after commaLee Leahy2017-03-0913-18/+18
| | | | | | | | | | | | | | Fix the following error detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) TEST=Build and run on Galileo Gen2 Change-Id: I297bfc3d03dc95b471d3bb4b13803e81963841b5 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18647 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* src/include: Indent code using tabsLee Leahy2017-03-0911-36/+36
| | | | | | | | | | | | | | | Fix the following error and warning detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line TEST=Build and run on Galileo Gen2 Change-Id: I487771b8f4d7e104457116b772cd32df5cd721a6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18646 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* src/include: Add do { } while(0) around macrosLee Leahy2017-03-091-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following error detected by checkpatch.py: ERROR: Macros with multiple statements should be enclosed in a do - while loop False positives are generated when assembly code is used in a macro. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define post_code(value) \ + movb $value, %al; \ + outb %al, $CONFIG_POST_IO_PORT False positives are also generated for linker script include files. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define SET_COUNTER(name, addr) \ + _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ + . = addr; False positives are also generated for attribute macros. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function)); TEST=Build and run on Galileo Gen2 Change-Id: I88abf96579e906f6962d558a3d09907f07d00b1c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* src/include: Move trailing statements to next lineLee Leahy2017-03-092-4/+8
| | | | | | | | | | | | | | Fix the following error detected by checkpatch.pl: ERROR: trailing statements should be on next line TEST=Build and run on Galileo Gen2 Change-Id: I169f520db6f62dfea50d2bb8fb69a8e8257f86c7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18643 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* src/include: Fix unsigned warningsLee Leahy2017-03-0917-133/+145
| | | | | | | | | | | | | | | | | | Fix warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' BRANCH=none BUG=None TEST=Build and run on Galileo Gen2 Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18607 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/skylake: Add GPIO macros for IOxAPIC and SCILi Cheng Sooi2017-03-091-0/+11
| | | | | | | | | | | | | | | | Add two GPIO macros: 1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the APIC with input assuming the events are edge triggered. 2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose input to SCI assuming the events are level triggered. Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* soc/intel/skylake: Add SKL SOC PCH H GPIO supportLi Cheng Sooi2017-03-095-194/+510
| | | | | | | | | | | | | | | | Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H specifications to support sklrvp11. Split the gpio_defs.h into headers gpio_pch_h_defs.h and gpio_soc_defs.h for PCH-H specific and SOC specific GPIO defs respectively. Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2 Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com> Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18027 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* AGESA: Use printk for IDS outputKyösti Mälkki2017-03-094-60/+17
| | | | | | | | | | | | | | | | | | | In all simplicity, with board/OptionsIds.h file having: IDSOPT_IDS_ENABLED TRUE IDSOPT_TRACING_ENABLED TRUE And src/Kconfig modified to: config WARNINGS_ARE_ERRORS default n With these settings AGESA outputs complete debugging log where-ever you have your coreboot console configured. Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15320 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
* AGESA f15: Disable IDS tracing by defaultKyösti Mälkki2017-03-092-3/+2
| | | | | | | | | | | We build with WARNINGS_ARE_ERRORS, while IDS tracing will raise various (non-fatal) printk() format warnings. Change-Id: I9dc81c89ee60d17a6556a412380fed1413af66bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18560 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* AGESA: Make eventlog more tolerant to failuresKyösti Mälkki2017-03-096-0/+54
| | | | | | | | | | | | | | We have been forced to build AGESA with ASSERT() as non-fatal for some board, as hitting those errors is not uncommon. For the cases touched here, abort eventlog operations early to avoid further errors and dereference of null pointers. Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18543 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* AGESA: Fix loop condition for eventlog readKyösti Mälkki2017-03-091-3/+4
| | | | | | | | | | | | Do not evaluate AmdEventParams if AmdReadEventLog() fails. Change-Id: I2b8afe827ffe6757e64c00ab005d3bb8cc577321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18611 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
* AGESA: Apply a threshold on event loggingKyösti Mälkki2017-03-096-0/+18
| | | | | | | | | | | | Implement threshold as described in AMD.h, and do not add entries below STATUS_LOG_LEVEL in the eventlog. Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18542 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* AGESA: Log heap initialisationKyösti Mälkki2017-03-091-0/+6
| | | | | | | | | | | This is useful for debugging S3 issues and in general to understand AGESA memory allocator behaviour. Change-Id: I422f2620ed0023f3920b8d2949ee1c33a6c227e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18535 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
* AGESA: Log if memory training result cannot be storedKyösti Mälkki2017-03-091-0/+5
| | | | | | | | | | | | | | A problem around CAR teardown time may result with missing training results at the time we want to save them. Record this in the logs for debugging purposes, it will not be possible to use S3 suspend if this happens. Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18534 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* AGESA: Fix SSE regression and align stack earlyKyösti Mälkki2017-03-091-2/+6
| | | | | | | | | | | | | | | | | | | | | When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. Fixes regression with new toolchain using GCC-6.3 and ec0a393 console: Enable printk for ENV_LIBAGESA For some builds, the above-mentioned commit emitted SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18622 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* toolchain: fix compilation of GMP on FreeBSDIdwer Vollering2017-03-091-0/+20
| | | | | | | | | | | | | Built on FreeBSD -CURRENT Obtained from FreeBSD: https://github.com/freebsd/freebsd-ports/commit/bbedec80e36fe22a4f55433c3e6c2a64828fd9da Change-Id: Ic6b6db8e3a9d86a30c50a09d58566846446031ea Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/18675 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* cpu/intel/model_6{e,f}x: Unify init filesPaul Menzel2017-03-092-10/+12
| | | | | | | | | | | | | The init files for the Core Duo and Core 2 Duo are very similar. Reduce the differences, by using the same order for the include statements, the same blank lines, and the same comments. Change-Id: I0de060222a61a482377c760c6031d73c7e318edf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18506 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* mainboard/google/poppy: Enable cros_ec_keyb deviceFurquan Shaikh2017-03-091-0/+2
| | | | | | | | | | | | | | | | This is required to transmit button information from EC to kernel. BUG=b:35774934 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I8f380f935c2945de9d8e72eafc877562987d02db Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18642 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* google/chromeec: Add support for cros_ec_keyb deviceFurquan Shaikh2017-03-091-0/+9
| | | | | | | | | | | | | | | | | | This is required to pass button information from EC to kernel without using 8042 keyboard driver. 1. Define EC buttons device using GOOG0007 ACPI ID. 2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE. BUG=b:35774934 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* soc/intel/apollolake: Add check if FPFs are blownAndrey Petrov2017-03-091-1/+116
| | | | | | | | | | | | | Apollolake platform comes with FPF (field-programmable-fuses). FPF can be blown only once, typically at the end of the manufacturing process. This patch adds code that sends a request to CSE to figure out if FPFs have already been blown. Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18604 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* soc/intel/apollolake: Start using common CSE driverAndrey Petrov2017-03-091-0/+2
| | | | | | | | Change-Id: If866453f06220e0edcaa77af5f54b397ead3ac14 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18603 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* soc/intel/common/block: Add HECI driverAndrey Petrov2017-03-094-0/+536
| | | | | | | | | | | | | | | | | Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* soc/intel/apollolake: Prepare to use common HECI driverAndrey Petrov2017-03-094-4/+6
| | | | | | | | | Change-Id: Ib284493d886b223e8c85607de5fdb56b698fe5fa Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* uti/lint/checkpatch: Fix __attribute__ struct errors for OPEN_BRACEMartin Roth2017-03-091-0/+1
| | | | | | | | | | | | | | The __attribute__((weak)) lines on structs were being read as functions, causing a warning that the brace should be on the next line. Add a check to see if it's a struct with an attribute, and ignore it for the OPEN_BRACE check if it is. Change-Id: Ieb0c96027e8df842f60ca7c9de7aac941eed1dc2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18570 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
* checkpatch.conf: Update rulesMartin Roth2017-03-091-0/+5
| | | | | | | | | | | | | | | | | | - Remove the "MISSING_SPACE" check which checks for breaks at a space in a string concatenation. Most of the time this makes sense, but we occasionally need to break where there isn't a space, so having a hard rule doesn't always work. - Don't check the vendorcode directory for compliance to coreboot's code format rules. Change-Id: Ic07677b19520b5d22363834c77f5dee7bba9e429 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18569 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
* uti/lint/checkpatch: add --exclude to ignore specific directoriesMartin Roth2017-03-091-0/+13
| | | | | | | | | | | | | | | | | | | | checkpatch: add option for excluding directories when importing code from external sources Using --exclude <dir> we should be able to exclude a list of well defined locations in the tree that carry sources from other projects with other styles. This comes from the 01org/zephyr project in github: Original-Change-Id: I7d321e85eed6bc37d5c6879ae88e21d20028a433 Original-Signed-off-by: Anas Nashif <anas.nashif@intel.com> Change-Id: Icc9e841e7d84026d6ab857ff90b0f093515ccaad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18568 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
* src/lib: Remove spaces after ( and before )Lee Leahy2017-03-094-10/+10
| | | | | | | | | | | | | | | | | Fix the following errors detected by checkpatch.pl: ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' TEST=Build and run on Galileo Gen2 Change-Id: I586c5731c080282080fe5ddf3ac82252cb35bdd4 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18636 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mainboard/google/poppy: Add EC_HOST_EVENT_MODE_CHANGE to wakeup sourceFurquan Shaikh2017-03-081-2/+6
| | | | | | | | | | | | | | | Allow EC mode change event to wake AP up in S3. BUG=b:35775085 BRANCH=None TEST=Compiles successfully for poppy. Change-Id: I6f1546c60aef6620e22cdce2fab3a2709e6556a1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18608 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* chromeos/elog: Filter developer mode entry on S3 resumeDuncan Laurie2017-03-081-2/+17
| | | | | | | | | | | | | | | | | | | | The event log entry indicating developer mode is useful for the boot path, but is not really useful on the resume path and removing it makes the event log easier to read when developer mode is enabled. To make this work I have to use #ifdef around the ACPI code since this is shared with ARM which does not have acpi.h. BUG=b:36042662 BRANCH=none TEST=perform suspend/resume on Eve and check that the event log does not have an entry for Chrome OS Developer Mode. Change-Id: I1a9d775d18e794b41c3d701e5211c238a888501a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18665 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* intel/skylake: Filter suspend well power failure event for Deep SxDuncan Laurie2017-03-081-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | If Deep Sx is enabled the event log will get entries added on every power sequence transition indicating that the suspend well has failed. When a board is using Deep Sx by design this is intended behavior and just fills the logs with extraneous events. To make this work the device init state has to be executed first so it actually enables the Deep Sx policies in the SOC since this code does not have any hooks back into the devicetree to read the intended setting from there. BUG=b:36042662 BRANCH=none TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and then check the event log to be sure that it does not contain the "SUS Power Fail" event. Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18664 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* intel/skylake: Add function to read state of Deep S5Duncan Laurie2017-03-081-0/+8
| | | | | | | | | | | | | | | | | | | Add a function to read the current state of Deep S5 configuration and indicate if it is enabled (for AC and/or DC) or disabled. This is similar to the existing function that checks Deep S3 enable state. BUG=b:36042662 BRANCH=none TEST=tested with subsequent commits to check Deep S5 state at boot and filter event log messages if it is enabled. Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/skylake: Add devicetree settings for acoustic noise mitigationDuncan Laurie2017-03-082-0/+38
| | | | | | | | | | | | | | | | | | | | Add options to the skylake chip config that will allow tuning the various settings that can affect acoustics with the CPU and its VRs. These settings are applied inside FSP, and they can adjust the slew slew rate when changing voltages or disable fast C-state ramping on the various CPU VR rails. BUG=b:35581264 BRANCH=none TEST=these are currently unused, but I verified that enabling the options can affect the acoustics of a system at runtime. Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* google/eve: Configure GPIOs for new boardDuncan Laurie2017-03-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | A new board revision is making use of two previously unused GPIOs to drive BOOT/RESET pins to an on-board MCU. The reset pin is open drain so it is set as input by default, and the boot pin is driven low by default. Since these are UART0 pins they also need to be set up again after executing FSP-S as it will change them back to native mode pins. BUG=b:36025702 BRANCH=none TEST=manual testing on reworked board, toggling GPIOs to put the MCU into programming mode. Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* libpayload-x86: Enable SSE and FPU when presentPatrick Rudolph2017-03-081-0/+43
| | | | | | | | | | | | | | | Allows to use SSE and floating point in payloads without digging to much into x86 assembly code. Tested on Lenovo T500 (Intel Core2Duo). Both floating point operation and SSE is properly working. Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18345 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* nb/intel/nehalem/raminit.c: Refine broken commentStefan Tauner2017-03-081-2/+2
| | | | | | | | | | Change-Id: Ic5c92d9a2d8bb040a04602e5da2cd37a2ae8db95 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/18052 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Martin Roth <martinroth@google.com>
* mainboard/google/snappy: Override USB2 phy settingWisley Chen2017-03-081-0/+6
| | | | | | | | | | | | | | | | | | Fine tune USB2, need to override the following registers. port#1: PERPORTPETXISET=7 PERPORTTXISET=0 BUG=b:35858164 BRANCH=reef TEST=built, measured eye diagram on snappy, and reviewed by intel Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18590 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* util/intelmetool: Add support for Wildcat Point LPHuan Truong2017-03-081-4/+6
| | | | | | | | | | | | | | This adds support for the Wildcat Point LP for intelmetool. When the tool detected a Wildcat Point LP, then the ME will be reported as difficult-to-remove. Change-Id: I35423db11cdc1e21e7f02ce90dace7fb4d236c45 Signed-off-by: Huan Truong <htruong@tnhh.net> Reviewed-on: https://review.coreboot.org/18575 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* util/intelmetool: Fix segfault on edge casesHuan Truong2017-03-081-1/+2
| | | | | | | | | | | | | | | | | The intel ME checker tool would segfault if it reaches the end of the loop without having the dev pointer set. This happens when it gets to the end of the previous loop without knowing what to do with any of the devices it sees. This patch makes sure the pointer is not NULL before accessing it. Change-Id: Ia13191799d7e00185947f9df5188cb2666c43e2a Signed-off-by: Huan Truong <htruong@tnhh.net> Reviewed-on: https://review.coreboot.org/18573 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* MAINTAINERS: Update listMartin Roth2017-03-081-6/+22
| | | | | | | | | | | | | | | - Fix whitespace: Change some spaces to tabs - Add myself as an abuild maintainer - Add util/xcompile and util/genbuild_h to the BUILD SYSTEM section - Add new sections for utilities: docker, toolchain, and git - Remove GENERIC DRAM section - Remove the mailing list. We don't want it to be added as a reviewer. Change-Id: I78692fcac174d7b7c4d65911c85e4e2dacefcfc0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* binaryPI platforms: Drop any ACPI S3 supportKyösti Mälkki2017-03-088-576/+0
| | | | | | | | | | | | | | | | | | | | | | | | No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18501 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* binaryPI boards: Drop any ACPI S3 supportKyösti Mälkki2017-03-0814-197/+65
| | | | | | | | | | | | | None of the boards currently have HAVE_ACPI_RESUME and and ACPI S3 support calls should not appear under board directories anyways. Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18500 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* AGESA fam10: Add missing includeKyösti Mälkki2017-03-081-0/+1
| | | | | | | | | | The file is used for fam15. Change-Id: I7cdf238a8f7be4bf79546bcfc3c9d05bd8986e3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18635 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* AGESA: Move heap allocator declarationsKyösti Mälkki2017-03-086-18/+23
| | | | | | | | | | | | | Definitions are not part of ACPI S3 feature, nor do they require any AGESA headers so move them to a better location. Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* AMD geode: Avoid conflicting main() declarationKyösti Mälkki2017-03-0824-24/+28
| | | | | | | | | | | | | Declaration of main in cpu/amd/car.h conflicts with the definition of main required for x86/postcar.c in main_decl.h. Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18615 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mainboard/asus: Move F2A85-M_LE variant to F2A85-M.Kyösti Mälkki2017-03-0833-724/+75
| | | | | | | | | | | Note that M and M_PRO had same DefaultPlatformMemoryConfiguration defined, use one for both. Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18606 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* amd/pi/hudson: Move APIC enable to CPU fileMarshall Dawson2017-03-075-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18436 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* amd/pi/hudson/acpi: Only declare S3 if it is supportedMarc Jones2017-03-071-0/+2
| | | | | | | | | | | | Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME is set. Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18493 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* amd/pi/hudson: Add early SPI setupMarshall Dawson2017-03-072-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | Add some generic functions that can configure the SPI interface to have faster performance. Given that the hudson files are used across many generations of FCHs, make sure to refer to the appropriate BKDG or RRG before using the functions. Notable differences: * Hudson 1 defines read mode in CNTRL0 differently than later gens * Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows setting FastSpeed as well * Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100 controller Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0) Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18442 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* amd/pi/hudson: Add SPI definitions to headerMarshall Dawson2017-03-071-0/+38
| | | | | | | | | | | | | | | Add defines that will be used later for setting the fastest settings in the SPI controller. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c) Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18441 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* amd/pi/hudson: Consolidate BITn definitionsMarshall Dawson2017-03-072-67/+33
| | | | | | | | | | | | | | | Remove unused definitions from a .c file and use the BIT(n) macro found in types.h instead. Convert existing definitions to BIT(n). Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c) Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18440 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 08:14:05 +0000