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* mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee2022-03-0210-14/+80
| | | | | | | | | | | | | | | | | | | | | | In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/docker/coreboot-jenkins-node: Alphabetize installed toolsMartin Roth2022-03-021-10/+21
| | | | | | | | | | | | | | It's easier to read and to add new packages when each package is on its own line and they're sorted alphabetically. Indenting them also makes it easier to see what's getting installed and what's a command. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62446 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/docker/coreboot-jenkins-node: add linkcheckerMartin Roth2022-03-021-0/+1
| | | | | | | | | | | | The linkchecker tool is now being used to find broken links in our websites. Since it's not needed for building anything, just add it to the jenkins-node Dockerfile instead. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iac2246b5378e556b5cd9f2107fc5a7e51d583b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62445 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/vell: Remove Rcomp settingsGaggery Tsai2022-03-021-7/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch removes Rcomp settings. In MRC design, it checks if the Rcomp settings from the board is 0 or null, if so, it uses the recommended Rcomp values. Otherwise, it uses the Rcomp settings passed from the UPD. From the change history of MRC, we're chasing a moving target. This RCOMP setting in coreboot is an old setting while the Rcomp settins in MRC are optimized settings. Moving forward, if there is a new stepping, it might be changed again which increases the maintenance effort in coreboot. IMHO, we should let MRC to set the optimized RCOMP values for the design. BUG=b:219378758 TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are filled properly by MRC. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/primus{4es}: modify GPP_B3 as unlockedCasper Chang2022-03-022-2/+6
| | | | | | | | | | | | | | | | | | | With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after warm reboot. Config GPP_B3 unlocked to make reboot works on primus. Also set GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power on sequence. BUG=b:221488504 TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage test reboot 30 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/amd/common/fsp/fsp_validate.c: print warning instead of errorJulian Schroeder2022-03-011-1/+1
| | | | | | | | | | | | | If an AMD FSP binary has no valid image revision information, print a warning instead of an error. Change-Id: Ie9c5a387b81205fe93382778090260e41e261776 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/chausie: Always enable developer modeRaul E Rangel2022-03-011-0/+2
| | | | | | | | | | | | | | | Chausie doesn't have recovery mode buttons so it's impossible to manually enter recovery mode to enable developer mode. This means we need to force developer mode. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* security/tpm: Add vendor-specific tis functions to read/write TPM regsTim Wawrzynczak2022-03-011-0/+28
| | | | | | | | | | | | | | In order to abstract bus-specific logic from TPM logic, the prototype for two vendor-specific tis functions are added in this patch. tis_vendor_read() can be used to read directly from TPM registers, and tis_vendor_write() can be used to write directly to TPM registers. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I939cf5b6620b6f5f6d454c53fcaf37c153702acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/tpm/spi: Convert static functions to enum cb_err return typesTim Wawrzynczak2022-03-011-73/+71
| | | | | | | | | | | | | | Instead of using raw integers to indicate success/failure, enum cb_err can be used to makes things clearer, so this patch converts most functions to return that instead of int. TEST=boot to OS on google/dratini, no TPM errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifb749c931fe008b16d42fcf157af820ec8fbf5ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/guybrush/var/nipperkin: update thermal settingKevin Chiu2022-03-011-1/+23
| | | | | | | | | | | | | | | | Enable STT and decrease sustained_power_limit_mW to 12W BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* intelblocks/cse: Skip sending EOP during S3 resumeMAULIK V VAGHELA2022-03-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | coreboot should skip sending EOP during S3 resume since CSE doesn't require EOP in resume path. Currently EOP is being sent during PAYLOAD_BOOT or PAYLOAD_LOAD stage which doesn't get called during S3 resume. In case EOP is moved in earlier stage, coreboot might send EOP in S3 resume as well. This patch adds check before calling cse_send_eop. BUG=b:211085685 BRANCH=None TEST=Check by moving EOP to earlier stage. EOP sending is skipped during S3 resume. Change-Id: I8f22446974bc1e7b2d57468633c36bb99ffe1436 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* Documentation/mainboard: Move flashing instructions to common dirSean Rhodes2022-03-013-70/+73
| | | | | | | | | | | Move the instructions for flashing coreboot with fwupd to common directory as the process is identical across all models and variants. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I293acf962b32c81fdf482e0df15363e1cffa39bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite: Add StarLite Mk IIISean Rhodes2022-03-0126-0/+1615
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ec/starlabs/merlin: Remove unused keyboard.aslSean Rhodes2022-03-011-59/+0
| | | | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ife0f5b8b6102b543a7ace6739fa44d32ca80dcde Reviewed-on: https://review.coreboot.org/c/coreboot/+/62333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* ec/starlabs/merlin: Add spaces to adhere to coding styleSean Rhodes2022-03-015-24/+23
| | | | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e965513d5888398834cab8c8445e97372f2b115 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/intel/adlrvp: Enable eMMC device for ADL-N RVPKrishna Prasad Bhat2022-03-012-0/+31
| | | | | | | | | | | | | | Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder Lake N RVP from devicetree. Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* Update fsp submodule to upstream masterMartin Roth2022-03-011-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating from commit id 10eae55: 2021-08-24 21:11:18 +0800 - (Elkhart Lake MR1 FSP) to commit id f4bbf5a: 2022-01-29 00:32:47 +0800 - (Apollo Lake MR10 FSP) This brings in 20 new commits: f4bbf5a Apollo Lake MR10 FSP aab8be0 Apollo Lake MR10 FSP 45b935f Apollo Lake MR10 FSP 755e782 Signed-off-by: Wong <swee.heng.wong@intel.com> da956c1 Whitley FSP 2.2.0.3A 7e3d894 Whitley FSP 2.2.0.3A 04ad3cd Tiger Lake - UP3 IoT FSP MR4 ccf7f35 Elkhart Lake MR2 FSP 4aa1275 Elkhart Lake MR2 FSP 8aa6a9a Cedar Island FSP 2.2.0.3A 2e2e740 Whitley FSP 2.2.0.3A 91a6117 Tiger Lake - UP3 IoT FSP MR3 2863499 Delete FspUpd.h df41c58 Delete FsptUpd.h 0d420eb Delete FspsUpd.h 53cc56a Delete FspmUpd.h ad51318 Tiger Lake - UP3 IoT FSP MR3 63273a4 Delete Fsp.fd ce61eb3 Tiger Lake - UP3 IoT FSP MR3 f7f77a2 Delete Fsp.bsf Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6128b9703498dd36be73c19cbbfe349c206c6cf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* lib/Makefile: Add ability to specify -ldflags for rmodulesRaul E Rangel2022-02-281-1/+1
| | | | | | | | | | | | | This will allow linker flag customization for rmodules. BUG=b:221231786 TEST=Build guybrush with patch train and verify ldflags are passed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib65476759e79c49d90856dcd7ee76d7d6e8a679a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Makefile: Add a build target for .mapRaul E Rangel2022-02-281-2/+5
| | | | | | | | | | | | | | | | We don't currently have a build target defined for .map files. This means they can't be used as a dependency. This change splits the .map creation into its own rule. BUG=b:221231786 TEST=Build guybrush and verify .map still exists Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1ce21902e97390aa9520670299ef08debf4458db Reviewed-on: https://review.coreboot.org/c/coreboot/+/62399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
* Makefile: Add .SECONDARYRaul E Rangel2022-02-281-0/+1
| | | | | | | | | | | | | | | | We currently delete intermediate files. This can make it difficult to debug and is also unexpected. Setting .SECONDARY will prevent make from deleting the files. BUG=b:221231786 TEST=Build guybrush with CL stack and see .map files are preserved Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I657a696acc71d42ba94442d4754ee63efd3e6a74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLYFred Reitberger2022-02-281-0/+7
| | | | | | | | | | | | Include chausie EC and EFS only in the RO region when building with vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B regions. Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Documentation: Fix broken link to Gerrit GuidelinesFelix Singer2022-02-281-1/+1
| | | | | | | | | Change-Id: I14084f95af122c160f287f0133017a769c249d00 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/common/block/acpi: Return existing Object for _DSM subfunctionTim Wawrzynczak2022-02-281-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Currently the LPIT Get Constraints _DSM subfunction returns a package containing the path to a nonexistent device (\NULL). This is used to work around an issue with Windows, where returning an empty package will cause a BSOD. However, using this non-existent device can also cause confusion, as on Linux, it shows an error in dmesg, e.g. ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \NULL (20200925/dspkginit-438) Therefore, this patch modifies this returned package slightly to include the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on Intel platforms that use the PEP driver. Tested on google/brya0 on ChromeOS 5.10 kernel Tested with current Windows 11 ISO Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
* cpu/x86/smm: Support PARALLEL_MP with SMM_ASEGArthur Heymans2022-02-283-3/+109
| | | | | | | | | | | | This will allow to migrate all platform to the parallel_mp init code and drop the old lapic_init code. Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58700 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/kano: add enable_off_delay_ms to 30David Wu2022-02-281-0/+1
| | | | | | | | | | | | | | | | Kano changes load switch of touch screen to TPS22914C (is not with discharge) on DVT board, EE suggests to add enable_off_delay_ms to 30ms to fix DUT can't enter S0ix issue. BUG=b:220811619 TEST=Boot kano to OS and run S0iX test 2500 cycles. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7ea5693d457c5f60246348d2d8fa1f4130b7d4c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
* mb/google/skyrim: Enable PCIe devices in devicetreeJon Murphy2022-02-281-0/+5
| | | | | | | | | | | BUG=b:214414301 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Enable AP <-> D2 communicationJon Murphy2022-02-285-2/+68
| | | | | | | | | | | | | | | | Configure D2 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for D2 device and enable the required config items. BUG=b:214414776 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Add eSPI configurationJon Murphy2022-02-282-0/+39
| | | | | | | | | | | BUG=b:214413613 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Add initial fch irq routingJon Murphy2022-02-281-0/+85
| | | | | | | | | | | BUG=b:214417045 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I6de1e4877323e18ec9d95f182c7d3fccd51d4998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Add initial I2C configurationJon Murphy2022-02-283-0/+36
| | | | | | | | | | | | | | Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. BUG=b:214414677 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Log mainboard events to elogJon Murphy2022-02-282-0/+8
| | | | | | | | | | | | BUG=b:214414851 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Add ACPI configuration for USB portsJon Murphy2022-02-281-2/+71
| | | | | | | | | | | | | | | | | | | The USB port configuration was derived from the PPR and schematics. This board has 6(some multi-purpose) ports. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras 1 Bluetooth transceiver BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Add XHCI configurationJon Murphy2022-02-284-12/+34
| | | | | | | | | | | | | | Add xhci 2 controller support for additional USB port/ Dummy setting BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* drivers/wwan/fm: Add support for _PTS for Fibocom 5G WWANCliff Huang2022-02-281-1/+18
| | | | | | | | | | | Add DPTS (device prepare to sleep) method that is to be called in mainboard's \_SB.MPTS, which is called in _PTS. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ie308f74940a33711a398bc11d0550cb06b55cdcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/pci_device: Fix PCIe bridge detectionNico Huber2022-02-281-0/+3
| | | | | | | | | | | | | | | | | | PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(), it's our virtual `domain` device. Expecting a PCI device above bus 0 resulted in undefined behavior for all boards with PCI. Only boards with a PCI device 00:00.0 that looked like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake). Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171 Signed-off-by: Nico Huber <nico.h@gmx.de> Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe) Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/kano: Add wifi sar tableDavid Wu2022-02-282-0/+8
| | | | | | | | | | | | | | 1. Add wifi sar table for kano 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:214393458 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Icddd583e5ee31e08b615df6fb2f4ceeb7f0c8131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
* sb/intel/lynxpoint: Fix up commentAngel Pons2022-02-281-2/+2
| | | | | | | | Change-Id: Ie46b63d192b8e4871442f6b0db5b1575168f89ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/google/dedede/var/pirika: Add Wifi SAR for pasaraFrank Chu2022-02-283-0/+25
| | | | | | | | | | | | | | | Add wifi sar for pasara BUG=b:216411442 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* Documentation/releases/index: Clean up documentFelix Singer2022-02-271-6/+6
| | | | | | | | | | | | There is no reason to use lists to link the checklist and template document. Thus, link to these documents in their related flowing text. Change-Id: I9bce0dd6595f1a208e7ea2311a653f9af32530de Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62412 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/releases: Move upcoming release section to the topFelix Singer2022-02-271-20/+20
| | | | | | | | | | | | | | | | | The list of releases will grow and in the current state each release moves the section for the upcoming release more down making it less visible. Thus, switch both sections, so that the documentation for the upcoming release is at the top. Also, invert the order of the previous releases, so that the latest is at the top. Change-Id: I69987e035f38ae3ca14dbf5c7644d5292106a978 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62411 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/releases: Move checklist and template to upcoming sectionFelix Singer2022-02-271-5/+6
| | | | | | | | | | | The documents for the checklist and template are related to upcoming releases. Thus, move them to the section for upcoming releases. Change-Id: Ibe6be506d2833036105b7c86445dca2a6efb7a55 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62410 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Rename release notes document titleFelix Singer2022-02-272-5/+5
| | | | | | | | | | | | The release notes document also contains information about upcoming releases, not only previous releases. Thus, rename the document in the main menu and give it a proper title. Change-Id: I4480c0b6e4be6fcbcb9a00beb0be169a7eed435d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Move Gerrit Guidelines to "Contributing" sectionFelix Singer2022-02-273-1/+1
| | | | | | | | | | | | | The Gerrit Guidelines are related to the contributing process and also contain documentation which goes beyond "Getting started". Thus, move them to the "Contributing" section. Change-Id: I775a79c14562a1f4a9563012aee3b690c0635cc1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* utils/cbfstool: Fix building with `make test-tools`Felix Singer2022-02-271-11/+13
| | | | | | | | | | | | | | The variable `RM` is empty and thus set it to `rm`. While executing the `clean` rule, run each `rm` command with the -f flag to ignore non-existing files. Also, disable the objutil feature locally fixing another build issue. Change-Id: Icb17e2c924ef480f8ac6195f96cf495709a0a023 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62415 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/testing: Add cbfstool tools to tested utilsMartin Roth2022-02-271-0/+1
| | | | | | | | | | | | Previously, cbfstool was tested as part of the coreboot build, but not tested individually. This let a change that broke elogtool slip through. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9e7b7a01d4a77ffdac932ba5af12cbd1ba96628b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Documentation/mainboard/ti: Fix Markdown linksFelix Singer2022-02-261-2/+2
| | | | | | | | Change-Id: I08351beccb5174494855eee32bccfbcef77b8346 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62385 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "util/cbfstool: Port elogtool to libflashrom"4.164.16_branchMartin Roth2022-02-264-254/+11
| | | | | | | | | | | | | | | | | | | | This reverts commit d74b8d9c990780ba64515b36aaff79d719d71ead. This change breaks the 'make all' build of the cbfstool tools from the util/cbfstool directory unless libflashrom-dev is installed, complaining that flashrom is not installed. Even with libflashrom-dev installed, it breaks building elogtool with the public version of libflashrom-dev. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I572daa0c0f3998e20a8ed76df21228fdbb384baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/62404 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable USB controllers in devicetreeJon Murphy2022-02-261-0/+4
| | | | | | | | | | | BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable internal graphicsJon Murphy2022-02-261-0/+3
| | | | | | | | | | | | BUG=b:214416935 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Enable console UARTJon Murphy2022-02-262-0/+2
| | | | | | | | | | | | BUG=b:214414501 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-01 09:41:52 +0000