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* mb/google/deltaur: Remove mainboard from treeTim Wawrzynczak2022-05-1237-1883/+0
| | | | | | | | | | | | This board never made it to production, and development on it has long since stopped; it is a maintenance burden, therefore drop it from the tree. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/amd/sabrina/fsp_m_params: fix modification of constantFred Reitberger2022-05-121-1/+4
| | | | | | | | | | | | mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is constant. Changing a constant is undefined behavior, so create a local static instance of usb_phy_config that can be modified safely. Change-Id: Iedbc49109dcd1da9198fcb2a8f84e2b567cd8f86 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64130 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSPFelix Held2022-05-121-16/+19
| | | | | | | | | | | | | | | This file started as a copy from Cezanne. Sabrina has less USB ports than Cezanne. Also the struct definition of fch_usb2_phy has changed and FSP_USB_STRUCT_MINOR_VERSION is also updated. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/64129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina/fsp_m_params: add defines for FSP USB struct versionFelix Held2022-05-122-2/+5
| | | | | | | | | | | | | Add and use defines instead of magic values in fsp_m_params.c. The values will be updated to match the Sabrina FSP in a follow-up commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/64128 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/sabrina/fsp_m_params: don't hard-code USB PHY config table sizeFelix Held2022-05-121-1/+2
| | | | | | | | | | | Use sizeof instead of having a hard-coded struct length. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c39d770a7719e30572e71b6a6c24fa2ad4a9426 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Makefile.inc: Remove leftoverArthur Heymans2022-05-121-1/+1
| | | | | | | | | | | Commit 9a8d0a03db (crossgcc: Upgrade IASL from 20211217 to 20220331) removed this parameter. Change-Id: Iba062efcabac88edc1f7937b75ea9d5d884b448b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/corsola: Enable TPM_GOOGLE_TI50Yu-Ping Wu2022-05-121-1/+1
| | | | | | | | | | | | | | Replace TPM_GOOGLE_CR50 with TPM_GOOGLE_TI50. BUG=b:232066387 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I0cc787b3104bc47f6f856497bbc0870e0519dc28 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64252 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/skyrim: Add USB WWAN configurationKarthikeyan Ramasubramanian2022-05-122-1/+18
| | | | | | | | | | | | | | | | | | Add Fibcom FM101-GL USB WWAN configuration with the required power sequence as suggested in Fibocom FM101-GL Hardware Guide V1.0. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the WWAN module is enumerated in the output of lsusb. localhost ~ # lsusb Bus 004 Device 003: ID 2cb7:01a2 Fibocom Wireless Inc. Fibocom FM101-GL Module Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I39f8e7204e31d9a4d093aacd838a18e6d2f44970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64004 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/skyrim: Add VL822 USB hubKarthikeyan Ramasubramanian2022-05-123-12/+43
| | | | | | | | | | | | | | | | In Skyrim, USB-A port and WWAN modules are connected to the SoC USB ports through an external hub. Update the USB configuration in the devicetree accordingly. Enable the ACPI driver for external USB hub. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the hub and USB-A ports are enumerated correctly in the output of lusub command. Change-Id: Ibf6a3da8add7361fc50adcf7c62e46df234685dc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63586 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/usb: Add chip driver for external USB hubKarthikeyan Ramasubramanian2022-05-124-0/+109
| | | | | | | | | | | | | | | Add chip driver for soldered down external USB hub. This driver adds ACPI objects for the hub and any downstream facing ports. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the hub and any configured ports have ACPI devices defined in SSDT. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I11d7ccc42d3dce8e136eb771f120825980e5c027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63968 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brask/variants/moli: Set GPP_E14 as the default value.Raihow Shi2022-05-121-2/+0
| | | | | | | | | | | | | | We found HDMI-DDIA didn't get hot plug detection,so set GPP_E14 as the default value to let HDMI-DDIA get hot plug detection. BUG=b:231769129 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1b5cc1465fec519be4bbe5e027be0dc25815f4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/64138 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/craask: Add supported touchpadTyler Wang2022-05-121-0/+9
| | | | | | | | | | | | | | | Add related settings for synaptics touchpad. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3b3bb5cec56901dadaaa1c5699781df45c237257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* include/memory_info.h: Increase DIMM_INFO_TOTAL to 32Johnny Lin2022-05-121-1/+1
| | | | | | | | | | | | | | | For multiple sockets platform 16 may not be enough, so increase it to 32. Tested=On a platform that has more than 16 memory DIMM, SMBIOS type 17 can show all DIMM tables. Change-Id: If72a8622ac1e7e67646aa4dd24b99637fb8b1297 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: lichenchen.carl <lichenchen.carl@bytedance.com>
* mb/starlabs/labtop: Enable Max Charge for CMLSean Rhodes2022-05-121-0/+1
| | | | | | | | | | | Enable the max charge feature for cml, as the EC supports it since Star Labs EC firmware 1.06. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I779a686960b63025fb5f40e826ed117f402a0b2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin: Remove offset for Max Charge when not supportedSean Rhodes2022-05-123-3/+3
| | | | | | | | | | | | Set the MAX_CHARGE offset to dead_code_t for boards that don't support the function. The avoids erroneous values being written to the EC. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I306c8a60818b780ef3bfb842e7fcc4d8500d6b03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/brya/var/agah: Enable PCIe RP 3 for LANTony Huang2022-05-121-0/+6
| | | | | | | | | | | | | | | Using CLKREQ 4 and CLKSRC 4 BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* arch/x86: Add support for catching null dereferences through debug regsRobert Zieba2022-05-127-2/+486
| | | | | | | | | | | | | | | | | | | This commit adds support for catching null dereferences and execution through x86's debug registers. This is particularly useful when running 32-bit coreboot as paging is not enabled to catch these through page faults. This commit adds three new configs to support this feature: DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and DEBUG_NULL_DEREF_HALT. BUG=b:223902046 TEST=Ran on nipperkin device, verifying that HW breakpoints work as expected. Change-Id: I113590689046a13c2a552741bbfe7668a834354a Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/non-car: Don't add bootblock cbfs fileArthur Heymans2022-05-121-0/+4
| | | | | | | | | | | | | The bootblock.elf file gets embedded in the BIOSPSP part and loaded by the PSP in dram. The top aligned bootblock in cbfs is unused. Tested on Cezanne/Guybrush. Change-Id: I72f0092e0e3628b388f6da6a417c2857a510b187 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/apl: Write to cbfs regions using intermediate targetsArthur Heymans2022-05-121-4/+6
| | | | | | | | | | | This also adds messages when adding the files. Change-Id: Ie812084cc243a18cbc2913804ef2190dd9d6ed9b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* security/intel/cbnt/Makefile.inc: Improve build flowArthur Heymans2022-05-121-5/+8
| | | | | | | | | | | | | Using 'files_added::' is no longer needed as all files have already been added to the build. This has the advantage of showing all final entries in the FIT table and CBFS during the build process as adding the bpm to cbfs and fit is moved earlier. Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmeticsArthur Heymans2022-05-121-2/+1
| | | | | | | | | Change-Id: I41bbdabf7b846386651e64f4afb5b7b9fb38e1cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* soc/amd/*/Makefile.inc: Do some cosmeticsArthur Heymans2022-05-124-4/+4
| | | | | | | | | | | | The first target for the add_intermediate targets is always $(obj)/coreboot.pre. Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* Kconfig: Add an option to skip adding a cbfs bootblock on x86Arthur Heymans2022-05-123-1/+9
| | | | | | | | | | Some targets don't need this as the bootblock is loaded differently. Change-Id: Ia42448f7e9dd0635c72857fbc1fab54508932721 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Makefile.inc: Add x86 bootblock as a separate targetArthur Heymans2022-05-122-11/+8
| | | | | | | | | | | | | | Some platforms don't need a top aligned bootblock in cbfs like Intel APL or modern AMD platforms as the bootblock is loaded differently. So they don't need the top aligned cbfs bootblock. To not clutter the main make file move out adding the bootblock. Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Makefile.inc: Move adding bootblock on non-x86 targetsArthur Heymans2022-05-121-4/+6
| | | | | | | | | | This can be done in a separate Makefile target. Change-Id: I50eae4f00d171d26a221ca969086f4f294fa524b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Makefile.inc: Generate master header and pointer as C structsArthur Heymans2022-05-126-13/+75
| | | | | | | | | | | | | | | | | | | | | | | | The makefiles don't like cbfs file names with spaces in them so update the file name with '_' instead of spaces. To keep the master header at the top of cbfs, add a placeholder. This removes the need to handle the cbfs master header in cbfstool. This functionality will be dropped in a later CL. On x86 reserve some space in the linker script to add the pointer. On non-x86 generate a pointer inside a C struct file. As a bonus this would actually fix the master header pointer mechanism on Intel/APL as only the bootblock inside IFWI gets memory mapped. TESTED on thinkpad X201: SeaBIOS correctly finds the cbfs master header. Change-Id: I3ba01be7da1f09a8cac287751497c18cda97d293 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* commonlib: Add timestamp IDs for Chrome OS hypervisorMattias Nissler2022-05-111-2/+24
| | | | | | | | | | | | | | | | | | | Chrome OS is experimenting with a hypervisor layer that boots after firmware, but before the OS. From the OS' perspective, it can be considered an extension of firmware, and hence it makes sense to emit timestamp to track hypervisor boot latency. This change adds timestamp IDs in the 1200-1300 range for this purpose. BUG=b:217638034 BRANCH=none TEST=Manual: cbmem -a TS_CRHV_BOOT to add a timestamp, cbmem -t to verify that it got added to the timestamp table. Change-Id: If70447eea2c2edf42b43e0198b827c1348b935ea Signed-off-by: Mattias Nissler <mnissler@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/crota: enable wifi sarScott Chao2022-05-113-0/+14
| | | | | | | | | | | | BUG=b:216594621 BRANCH=brya TEST=build pass and SAR table be changed according to tablet/ desktop mode Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I62265e8931da48d20cf41e0c91ccb1a5b4bc1167 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Disable thunderbolt interfaceDtrain Hsu2022-05-111-0/+4
| | | | | | | | | | | | | | | | | Disable all of the TBT devices in devicetree since kinox doesn't support thunderbolt. The change also need to disable TBT in fitimage (chrome-internal:4731094). BUG=b:231654363 TEST=Build and run on DUT. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I944680dd1f41ac6f375015a3a138eb00c41b58a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brask/variants/moli: correct tcss_usb3 portCasper Chang2022-05-111-2/+2
| | | | | | | | | | | | | Correct tcss_usb3_port to meet Moli's schematic design. BUG=b:220814038 TEST=emerge-brask coreboot Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* device/dram/common.h: Use C over CPPArthur Heymans2022-05-111-5/+5
| | | | | | | | | | | This fixes building with clang. Change-Id: Ia8511ab46184aa0d8ee3a79c3ef22614aeb61298 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* amd/*/gcccar.inc: Replace local declarationsArthur Heymans2022-05-115-268/+187
| | | | | | | | | | | | | Although useful to declare local symbols inside macros clang does not support them. Using the \@ symbol which increments each time the macro is used we can do the same. With BUILD_TIMELESS=1 the binaries don't change and do build with GCC so nothing is lost here. Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libpayload/nvme: Fix controller disablement in (de)init sequenceNico Huber2022-05-111-2/+2
| | | | | | | | | | | | | | | We wrote to the wrong register. The EN bit is in the CC (Controller Configuration) register at 0x14. Fixes re-initialization in QEMU and on siemens/chili during a second FILO run. Change-Id: I125de55d7f1a7c9f070437190c5a08a288b274f8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libpayload/nvme: Test for NVMe-command-set bit individuallyNico Huber2022-05-111-1/+1
| | | | | | | | | | | | | | We only need to know if the NVMe command set is supported. Other command-set bits can be set too, but we don't have to care. Fixes init in QEMU which has more command-set bits set by now. Change-Id: I29a693cf8cc13775e94dc671e8d0412ad86fef9c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libpayload/nvme: Fix error paths of nvme_init()Nico Huber2022-05-111-11/+12
| | | | | | | | | | | | | | We mustn't try to release resources that we haven't acquired yet. Also, sending commands to the NVMe device is futile if we already timed out. Fixes hangs after a failed init noticed in QEMU and on siemens/chili. Change-Id: Ib83c7785d6e0dc3c44fbd50a30694c74932750d6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/*: Use __fallthrough statementArthur Heymans2022-05-112-3/+3
| | | | | | | | | | Clang needs an attribute not a comment. Change-Id: I78f87d80bd4f366ed6cfa74619dd107ac61bc935 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* *.h: Fix up typos in guardingArthur Heymans2022-05-114-4/+4
| | | | | | | | | | | Clang complains about this. Change-Id: I421d6c5daa373d1537e4ac2243438e7f1f6208d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63067 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sec/intel/txt: Use 'bios_acm_error' variableArthur Heymans2022-05-111-1/+1
| | | | | | | | | | | | | Use the variable intended for this use. This fixes building with clang. Change-Id: I4ee61fb9533b90ddb1a1592d5d9945761739ddb6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63062 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* superio/kbc1100: Fix set but unused variablesArthur Heymans2022-05-111-4/+0
| | | | | | | | | | | This fixes building with clang. Change-Id: I865038ffab9cd7be8aa6a42e629f108b55c08f59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* mb/*/bootblock.c: Fix set but unused variable over inb loopArthur Heymans2022-05-112-4/+3
| | | | | | | | | Change-Id: Iba80c4a5960c6fb59f542b33e8e769576ccfed59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* vendorcode/amd/cimx/sb900: Drop codeArthur Heymans2022-05-1140-15126/+0
| | | | | | | | | | No mainboard is using this code. Change-Id: I4374360c211593a8468b6226f3d1729885b533e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* amd/fam15tn/gcccar.inc: Fix msr access with clangArthur Heymans2022-05-111-2/+2
| | | | | | | | Change-Id: I21bebd475dce373a77626d2e78a0ab10678ea8b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* amd/f15tn/gcccar.inc: Fix macro with ClangArthur Heymans2022-05-111-1/+1
| | | | | | | | Change-Id: I0d95ac9d548e410a81188307cc92f77224baea0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* drivers/intel/gma/opregion.c: Fix uninitialised variable useArthur Heymans2022-05-111-2/+2
| | | | | | | | Change-Id: I87cff1e0360e23e37201381ed8a6920ee36b2747 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61892 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/usb/ehci_debug.c: Fix unused variable warningArthur Heymans2022-05-111-9/+8
| | | | | | | | | | | Clang complains about unused variables when DEBUG_CONSOLE_INIT is not set. Change-Id: Icf5fd69fbf54b0d40bfdb17d1396d77dcb0a6060 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* security/tpm/crtm.c: Remove set but unused variableArthur Heymans2022-05-111-6/+0
| | | | | | | | | Change-Id: I3c97cb57fe13adee217783973691748d6c542abe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Documentation: Add NovaCustom laptops to ships-with-coreboot hw listIgor Bagnucki2022-05-101-0/+9
| | | | | | | | | | Change-Id: Ic0fc521d13362b2f3047eb91af8d5b3ac74eaa1d Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* Documentation: Add Dasharo to after-market firmware listIgor Bagnucki2022-05-101-0/+9
| | | | | | | | | Change-Id: I19dbf70bc9ceec1408944c4029db6eabd5e2254d Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* soc/mediatek: Demote log level of SPMI clock calibration problem to infoRex-BC Chen2022-05-091-2/+2
| | | | | | | | | | | | | | | | It's expected that the mismatch logs will be shown when doing calibration for spmi clock. If it is failed to do calibration for spmi clock for all data, the system will enter "die". Therefore, we adjust the log level from BIOS_ERR to BIOS_INFO. BUG=b:231531254 TEST=emerge-cherry coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64090 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xFzhiyong tao2022-05-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot. Setting it to 0xA would cause an extra delay of 20ms compared to 0xF. The value of time slot is from 0x0 to 0x1F which represents the delay when reset occurs. To avoid the delay, change the value from 0xA to 0xF. This modification is based on chapter 3.7 in the MT8186 functional specification. BUG=b:218630683, b:218630684 TEST=the power-off waveform is correct. Signed-off-by: zhiyong tao <zhiyong.tao@mediatek.corp-partner.google.com> Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64038 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-28 23:04:05 +0000