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* MAINTAINERS: Update mainboardsMartin Roth2022-10-301-50/+8
| | | | | | | | | | | | | | | - AMD reference boards are maintained at least for odd fixes. - Google panther has become a variant of Beltino, so remove it. - Remove people whose email addresses are bouncing email. - Remove people who responded to my email about being a maintainer and asked to be removed. - Alphabetize list Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic6ecaae77df2f2edaf724160bce04c038cbd115e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* MAINTAINERS: Add orphaned mainboardsMartin Roth2022-10-301-0/+168
| | | | | | | | | | | | | | | | The mainboards are broken out into individual entries in hopes that it will be easier for someone to claim ownership than if they were lumped into a single "Orphaned Mainboards" group. The theory behind this is that a single mainboard is really the easiest piece of coreboot to maintain. Hopefully some less-experienced people will be interested in stepping up to take over ownership of a mainboard. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9542b3a7cd87fa8656bc0982c08061e9d0513745 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mainboard/amd/chausie: Don't use APCB_FT6_UpdatableNikolai Vyssotski2022-10-291-2/+2
| | | | | | | | | | | | This APCB binary is not used for coreboot builds. Coreboot does not support RW APCB. Change-Id: I4d317ae31cf226b5481619f1539abb6237033f7c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* Docs/releases: Update release checklist documentMartin Roth2022-10-291-83/+149
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9a79cf92620755e19266faaf593dc2657acdb16f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* soc/amd/common: Initialize STB Spill-to-DRAMMartin Roth2022-10-294-1/+54
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I547671d2bcfe011566466665b14e151b8ec05430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* commonlib...cbmem_id.h: Add AMD STB buffer IDs for CBMEMMartin Roth2022-10-291-1/+5
| | | | | | | | | | | - CBMEM_ID_AMD_STB Main Spill-to-DRAM buffer. 2 to 16MiB. - CBMEM_ID_AMD_MP2 Debug buffer. 128KiB Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I27157ad65df992bcdd0e0d15a6d01b96e24067c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB deviceFelix Held2022-10-296-30/+6
| | | | | | | | | | | | | | | | | | | | | | Don't set bit 2 in _STA in order for Windows not to show a warning about an unknown device in the device manager for this device. Since the _STA object just returns a constant, a name definition can be used instead of a method definition. TEST=The unknown device with device instance path ACPI\AAHB0000\0 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Just shutting down and then booting it again won't clear some internal state in Windows, so a reboot is needed instead for the change to become visible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* util/lint: fall back to regular grep in kconfig_lintSolomon Alan-Dei2022-10-291-1/+6
| | | | | | | | | | | Automatically fall back to using regular grep if working outside a git repository and the option to use regular grep is not specified Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com> Change-Id: I0cdecf01a0e74c30947c4fe7e7c7d9457a5165a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/starlabs/*: Change the local version to KconfigSean Rhodes2022-10-293-2/+6
| | | | | | | | | | Replace the string with a Kconfig option Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib11ddd04c44f47b94f4fc9eaed278d554d581b0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/siemens/mc_ehl: Remove spd.bin from CBFSWerner Zeh2022-10-2910-172/+1
| | | | | | | | | | | | | The SPD data for DRAM init has moved into the hwinfo data structure and is therefore not used from spd.bin anymore. spd.bin will not receive any updates, changes will only be done in hwinfo. There is no reason to keep spd.bin around so remove it for both variants. Change-Id: Ie6091b655ba7ff2e01b684266ce34b85593b8623 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/meteorlake: Move P2SB PCI resource into P2SB deviceSubrata Banik2022-10-294-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch ensures the P2SB PCI device resource is getting reserved so that the resource allocator is not assigning this resource to any other PCI device during the PCI enumeration. BUG=b:254207628 TEST=Able to ensure on the Google/Rex device, the PCI enumeration is not assigning the P2SB BAR (0xE000_0000) to TBT Root Port3. Instead the 0xE000_0000 address is being assigned to the P2SB PCI device. Without this patch: [SPEW ]     PCI: 00:07.3 resource base e0000000 size c200000 align 20 gran 20 limit ec1fffff flags 60080202 index 20 [DEBUG]      GENERIC: 1.0 [DEBUG]      NONE [SPEW ]      NONE resource base e0000000 size c200000 align 12 gran 12 limit ec1fffff flags 40000200 index 10 With this patch: [SPEW ]     PCI: 00:07.3 resource base e1000000 size c200000 align 20 gran 20 limit ed1fffff flags 60080202 index 20 [DEBUG]      GENERIC: 1.0 [DEBUG]      NONE [SPEW ]      NONE resource base e1000000 size c200000 align 12 gran 12 limit ed1fffff flags 40000200 index 10 ...... [DEBUG]     PCI: 00:1f.1 [SPEW ]     PCI: 00:1f.1 resource base e0000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0789b442af23f6be81c666e284633ef342dffe0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* soc/intel/common: Fix potential NULL pointer dereferenceShaik Shahina2022-10-291-1/+8
| | | | | | | | | | | | | BUG=NONE TEST=Boot to OS on Nivviks Change-Id: I154011963e945b54dfca07f884e473d44dc4e813 Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68903 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHzAlanKY Lee2022-10-291-1/+1
| | | | | | | | | | | | | | | | | Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to 382.9 kHz. BUG=b:255505160 BRANCH=firmware-brya-14505.B TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage measure by scope with skolas Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* acpigen: Always inline helper functionsJakub Czapiga2022-10-291-8/+8
| | | | | | | | | | | | | Acpigen inline helper functions are causing problems while compiling coreboot with function instrumentation. Sometimes functions are not inlined and are causing linking errors. Forcing inlining fixes problems like that, as these functions would normally be inlined anyway. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ibf747573940fe5e76199f327f4e5bc32b4f8c470 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* util/chromeos/extract_blobs: try using RW_MAIN_A region firstMatt DeVillier2022-10-291-18/+22
| | | | | | | | | | | | | | Since the RW firmware may contain newer/additional blobs than the RO COREBOOT region, try using it first, then fall back to COREBOOT and eventually BOOT_STUB if necessary. TEST=extract blobs from dedede and brya firmware images Change-Id: Ia01b37f8c410685de8a17ea4105ca671931a47c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/amd/birman: Update Birman to work with Morgana or GlindaMartin Roth2022-10-294-8/+245
| | | | | | | | | | | | Birman should work with either Morgana or Glinda SoCs, so configure the mainboard to allow building with either. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I56206cd9ad5db99c00b734430b250e04ea9e0609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* soc/amd/glinda: Don't add amdfw.rom to cbfs in SOC MakefileMartin Roth2022-10-291-5/+0
| | | | | | | | | | | | CB:66943 - commit 8d66fb1a705 (soc/amd: Add amdfw.rom in coreboot.pre) changed the build flow for the amd firmware binary after glinda was branched from morgana. Update glinda to match the other SoCs. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b0ccaa8c33e59f7146edd6a86f107480c152008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common: Add coreboot post codes to STBMartin Roth2022-10-283-0/+13
| | | | | | | | | | | Adding coreboot's postcodes to the smart trace buffer lets us see the entire boot flow in one place. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/mendocino: Add code for printing STB to boot logMartin Roth2022-10-284-0/+18
| | | | | | | | | | | This adds the mendocino specific code for printing the STB data to the boot log. It still needs to be enabled in the mainboard to be used. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common: Add code to print AMD STB to boot logMartin Roth2022-10-284-0/+112
| | | | | | | | | | | | | | | This allows platforms that support AMD's STB (Smart Trace Buffer) to print the buffer at various points in the boot process. The STB is roughly a hardware assisted postcode that captures the time stamp of when the postcode was added to the buffer. Reading from the STB clears the data. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8d78c0e86b244f3bd16248edf3850447fb0a9e2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/mendocino: Expand extra 5 DPTC thermal related profilesEricKY Cheng2022-10-281-0/+56
| | | | | | | | | | | | | | | Expand extra 5 DPTC thermal related profiles for Dynamic Thermal Table Switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* soc/intel/xeon_sp: Remove unused madt setup functionArthur Heymans2022-10-283-33/+0
| | | | | | | | Change-Id: I248974c5a88768ee12f63fa77f3fa67a72ea510e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* cpu/x86/mp_init.c: Use linked list data structuresArthur Heymans2022-10-281-6/+10
| | | | | | | | | | | There is no need to keep track of device structures separately. Change-Id: Ie728110fc8c60fec94ae4bedf74e17740cf78f67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim/var/winterhold: Update touchscreen devicetree settingEricKY Cheng2022-10-281-6/+6
| | | | | | | | | | | | | | | | | Update touchscreen setting. ELAN900C is the I2C over hid device with slave address 0x10. MELF0410 is the pure I2C device with slave address 0x34. The LCD team verification result is on b/251378772 comment#11. BUG=b:251378772 TEST=Build/boot ChromeOS on winterhold, ensure touchscreen is functional. Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I568346d2abc39d9427e49c3b21f38db0184b8b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* mb/google/skyrim/var/winterhold: Enable DPTC supportEricKY Cheng2022-10-282-1/+2
| | | | | | | | | | | | | Enable DPTC support for Winterhold BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I97c2d3ee29687cd8a9c459e90a45cef05ac4436b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* soc/amd/cezanne/Kconfig: Enable APOB_HASHFred Reitberger2022-10-281-0/+1
| | | | | | | | | | Enable the APOB_HASH feature. This improves boot times by ~9.5ms. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9261d101eb23465208affbf815385d3f1bdbcd69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/getac/p470: Use 'enum cb_err'Elyes Haouas2022-10-282-8/+12
| | | | | | | | | Change-Id: I9650fc672a94343472b44037f8a664d7d15aaf15 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
* mb/getac/p470: Remove unused 'ec_oem_write()'Elyes Haouas2022-10-282-8/+0
| | | | | | | | Change-Id: Ia955d8736f9b1835ad33ce43dfbbcd9b6a0a9db4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
* mb/getac/p470: Remove unused 'send_ec_oem_data_nowait()'Elyes Haouas2022-10-282-8/+0
| | | | | | | | Change-Id: If68629f22803ebd61cd00b76b9e61822178325f9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
* lint/checkpatch: consider leading + in the line length limit checkMichael Niewöhner2022-10-281-0/+1
| | | | | | | | | | | | | | | | The line length limit in coreboot's coding style guidelines applies to the final file, while checkpatch currently checks the patch line length. Since patches´ lines start with a `+` (only added content is checked), the line length being checked is one character longer than the actual content. Increase max_line_length by 1 to take this into account. Change-Id: I8da45bb0d5fbe7d0e12c8b181cf01e5685186bf6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory partsEricKY Cheng2022-10-283-2/+6
| | | | | | | | | | | | | | | | Update H58G56BK7BX068 and H58G66BK7BX067 support BRANCH=None BUG=b:243337816 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2aa6169c6e824318e738878f8cd19e76fcfd5713 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/brask/variants/moli: keep SAGV disableRaihow Shi2022-10-281-1/+0
| | | | | | | | | | | | | | | Since there is not too many low power requirement for moli and it is doing FSI firmware qual, so it is not critical to enable the SAGV and keep SAGV disable. BUG=b:254600066 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I4115b35fed35b74a307b08f7a10ebced2309297f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68898 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* spd/lp5: Re-generate the SPD dataEricKY Cheng2022-10-282-2/+2
| | | | | | | | | | | | | | | | Re-generate Hynix H58G66BK7BX067 and H58G56BK7BX068 data with current spd_tools. BUG=b:243337816 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I19ae0477dea64f2cdd37b6aa51eadd6957c54059 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* cpu/intel/common: Fix typecasting issueSridhar Siricilla2022-10-281-1/+1
| | | | | | | | | | | | | | | | | | | | The patch fixes the typecasting issue, that is conversion from 'int' to 'unsigned long long int'. This changes value from '0x8000 0000' to '0xFFFF FFFF 8000 0000'. During unit testing, the argument is getting changed to an unexpected number which is resulting to an exception when IA32_HWP_REQUEST MSR is updated. In this update, the MSR's reserved bits are getting updated, so this causes exception. TEST= Verified the code on the Gimble. No exception is seen after the fix. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I35d382c792b9df260381b7696f3bbff43d6c4dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vc/amd/fsp: Add Glinda directoryMartin Roth2022-10-276-0/+816
| | | | | | | | | | Copied from Morgana - Needs to be updated. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id3175e6e6b5c7210b7c29f30e21e5a66f234c52a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* mb/google/brya: Update Crota's ELAN touchscreen delay to 150 msPaz Zcharya2022-10-271-1/+1
| | | | | | | | | | | | | | | | | ELAN updated the datasheet of component 4599 (qualification 10511) to version 0.6 (upload date: Oct 24, 2022), decreasing i2c delay during power-on sequence from 300 ms to 150 ms. BUG=b:232893949 TEST=Manually checked touchscreen works after reboot and suspend (on kernel v5.10) Signed-off-by: Paz Zcharya <pazz@google.com> Change-Id: I17e1f7d419637f6dff4049484ce1836ad98017ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/68868 Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/brya/var/lisbon: use i2c1 for TPM for lisbonKevin Chiu2022-10-271-0/+1
| | | | | | | | | | | | | | This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the lisbon variant. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I16be50258db2111d22f7465458873e92f44c7dac Reviewed-on: https://review.coreboot.org/c/coreboot/+/68887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya: Update devicetree setting for lisbonKevin Chiu2022-10-271-2/+307
| | | | | | | | | | | | | update devicetree setting per the schematic BUG=b:246657849 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I4268a5b43690a22bb703337fed84b83c45da4ad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brask/var/lisbon: Update gpio tableKevin Chiu2022-10-272-0/+167
| | | | | | | | | | | | | Based on latest schematic to update the gpio table. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I531f9ca9f6902d3318e99dadb58a811a4686a6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/skyrim: Expand cbmem console bufferZheng Bao2022-10-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expand the size of cbmem console buffer from default value 0x20000 to 0x80000. Verified by running "cbmem -l" in Chromium OS shell. localhost ~ # cbmem -l CBMEM table of contents: NAME ID START LENGTH 0. FSP MEMORY 46535052 b97fe000 01000000 1. CONSOLE 434f4e53 b977e000 00080000 2. RW MCACHE 574d5346 b977d000 00000360 3. RO MCACHE 524d5346 b977c000 00000f20 4. FMAP 464d4150 b977b000 0000047c 5. TIME STAMP 54494d45 b977a000 00000910 6. VBOOT WORK 78007343 b9766000 00014000 7. RAMSTAGE 9a357a9e b9700000 00066000 8. ACPI BERT 42455254 b96fc000 00004000 9. CHROMEOS NVS 434e5653 b96fb000 00000f00 10. REFCODE 04efc0de b96ab000 00050000 11. MEM INFO 494d454d b96aa000 00000768 12. RAMOOPS 05430095 b95aa000 00100000 13. COREBOOT 43425442 b95a2000 00008000 14. ACPI 41435049 b957e000 00024000 15. TPM2 TCGLOG 54504d32 b956e000 00010000 16. SMBIOS 534d4254 b9566000 00008000 17. FSP RUNTIME 52505346 ba7febe0 00000004 18. POWER STATE 50535454 ba7feb80 00000060 19. ROMSTAGE 47545352 ba7feb60 00000004 20. EARLY DRAM USAGE 4544524d ba7feb40 00000008 21. ACPI GNVS 474e5653 ba7feb20 00000020 BUG=246268888 TEST=Skyrim Change-Id: I79205f31b4cc3276c1c213a171a6bf7e18d73a1c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* console/post.c: Sort includesElyes Haouas2022-10-271-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I3faa1baf41ff8f0447d18b131a9c9c225e9fc8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* cpu/x86/mp_init: adjust timeout for final SIPIJonathan Zhang2022-10-271-2/+3
| | | | | | | | | | | | | | | Adjust timeout for final SIPI to satisfy some to-be-launched server processors. Add a spew print to display how long it takes for the APs to be ready. This is intended to facilitate only troubleshooting and trend analysis. Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68262 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/haswell: Enable VBOOT_VBNV_FLASHYu-Ping Wu2022-10-273-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for Haswell. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL (see [2]). However, there seems to be no particular reason on those platforms. Flashconsole works on Broadwell, at least, and it writes to flash as early as bootblock. Therefore, remove BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES, so that VBOOT_VBNV_FLASH can be enabled. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 (CB:45740) drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config BUG=b:235293589 TEST=./util/abuild/abuild -t LENOVO_THINKPAD_T440P -a (with VBOOT) Change-Id: If1430ffd6115a0bc151cbe0632cda7fc5f6c26a6 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPLSubrata Banik2022-10-271-0/+1
| | | | | | | | | | | | | | | | | | | | | This patch helps to save 10.200ms of booting time without any issue seen during MP Init. All cores are out from reset and alive. Additionally, no performance degradation is observed while running benchmarks. Refer to Intel Technical White Paper number:751003 for more details. BUG=b:211770003 TEST=Able to boot to ChromeOS with all cores are enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* Revert "soc/intel/systemagent.c: Fix memory type reporting"Arthur Heymans2022-10-271-2/+5
| | | | | | | | | | | | | This reverts commit 9c2f3cc9d9b3b3b7cfe1e62a70ea3061ca6c15ac. This broke the smihandler for no clear reason on some platforms. Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/siemens/mc_apl2: Enable early POST through NC_FPGAJan Samek2022-10-273-0/+28
| | | | | | | | | | | | | | | | | | Enable early POST code output for this mainboard, using the NC FPGA device on PCIe. This requires the parent PCI bridge to be initialized early. BUG=none TEST=boot on siemens/mc_apl2 and observe whether the POST codes coming from before FSP-M init are visible Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/google/brya/gaelin: Change DDR4 from interleave to non-interleaveRaymond Chung2022-10-272-0/+41
| | | | | | | | | | | | | | | | | The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. BUG=b:255399229, b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and pass MRC memory training Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* Update vboot submodule to upstream mainJakub Czapiga2022-10-271-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating from commit id b827ddb9: 2022-09-01 06:37:33 +0000 - (tests: Ensure auxfw sync runs after EC sync) to commit id 148e5b83: 2022-10-25 09:36:59 +0000 - (Makefile: Fix and simplify the RUNTEST test wrapper) This brings in 28 new commits: 148e5b83 Makefile: Fix and simplify the RUNTEST test wrapper a9c47c41 futility/cmd_show: set uninitialized variable e18a6cda gscvd: presume GBB flags are zero when hashing the RO space contents 0b0aee9c gscvd: refactor discovering GBB in the image ff1749cb futility: add option to save ro_gscvd section in a blob 84c65cd3 vboot_reference: Check OS/firmware mismatch and report to UMA 9a1be550 cmd_update: avoid variable name aliasing d0f7fdf6 treewide: Fix copyrights and extra new lines at end of file 0ca75fd1 tpm_lite: Fix copyrights, line endings, extra new lines at end of file 4ca43a34 crossystem: arm: Retry if we fail to read a GPIO f1a7efc0 futility: updater: Scan patch files for the signer_config manifest 64803227 futility: updater: Support patching GSCVD 2aa69d0c futility: Remove validate_rec_mrc command 0ca7a9e4 firmware: host: futility: Add CBFS metadata hash support aaeb307f futility: Use ccd update mode for suzyq ti50 aa44b7cf vboot: gbb_flags_common should treat ccd_ti50 like ccd_cr50 ff8bb2d9 futility: Address double free 6a33a0fc treewide: Fix license headers to conform with linter b2b4f767 DIR_METADATA: Add V2 Test Plans. 5346938c futility gscvd: add option to print out root key hash 5790c0aa gscvd: add support for reading ranges from the image 499e5743 gbb_flags_common.sh: Restore tmpfile cleanup trap f3f9d2a6 scripts/OWNERS: Fix engeg email chromium -> google ce620761 tests: Remove --allow-multiple-definition linker option 956c2efb futility: Skip picking apart an x86 kernel if has the EFI stub 9f2e9804 Avoid build failures on recent distros 62cc7885 subprocess: Log subprocess arguments when running 3bd35108 2api: Add a new entry point for only loading and verifying the kernel Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I9a16d6e02cee34140ec375ed6166f47560459140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68540 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFSMeera Ravindranath2022-10-274-1/+34
| | | | | | | | | | | | | | | | | | | a) Add LTR disqualification in D3 to ensure PMC ignores LTR from UFS IP as it is infinite. b) Remove LTR disqualification in _PS0 to ensure PMC stops ignoring LTR from UFS IP during D3 exit. c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply this LTR WA. BUG=b:252975357 TEST=build and boot nirwen and see no issues in PLT runs Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/{adl, cmn}: Allow config to select the OCP workaroundSubrata Banik2022-10-273-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a config option for SoC code to choose the applicable SoC workaround. For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE` to apply UFS OCP timeout disable workaround. At present ADL SoC only selects so, and in future MTL and others should check with Intel prior selecting this kconfig. It's the placeholder to add more workaround in required going forward. BUG=none TEST=Able to build and boot Google/Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-27 17:49:01 +0000