summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* Doc/releases: Fix coreboot 4.15 release notesAngel Pons2021-11-111-2/+2
| | | | | | | | | | | | | | coreboot 4.15 has just been released, so it's neither "upcoming" nor "planned" anymore. Change-Id: I287e40deec5877764e511885e3268b606caff597 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59121 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/guybrush: Define ACPI Power Resources for FPMCUKarthikeyan Ramasubramanian2021-11-1110-180/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently all the power sequencing for FPMCU is done explicitly in different stages of coreboot. This can all be done by adding ACPI power resources for FPMCU and clean up the unused code. Here is the expected power sequence: PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL Reboot : Shutdown -> 200 ms delay -> PowerUp BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to unlock the system after the first login attempt. Ensure that the FP is able to wakeup the system. Observed that the power resource is added correctly in the FPMCU ACPI object Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 { PR01 }) Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot { PR01 }) PowerResource (PR01, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x0B) \_SB.STXS (0x20) \_SB.STXS (0x0B) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.CTXS (0x0B) \_SB.CTXS (0x20) } } Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* mb/google/brya/var/taeko: Enable CPU PCIE RP 1Joey Peng2021-11-112-2/+30
| | | | | | | | | | | | | Modify settings to enable CPU PCIE RP 1 according to schematics. BUG=b:205504257 TEST=emerge-brya coreboot and can successfully boot with ssd and emmc. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/guybrush/dewatt: update dewatt configChris.Wang2021-11-111-0/+50
| | | | | | | | | | | | | | copy config from guybrush reference board. BUG=b:204151079 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* mb/google/brya/var/gimble: Improve USB2 eye diagram of DB Type-C portMark Hsieh2021-11-111-0/+1
| | | | | | | | | | | | | | - Set MAX OC1 to USB2_C1 BUG=b:205676803 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Idcf13ad072ae5d7a897f54adb19e6b2b068609dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* amdfwtool: Pack out-of-bounds check into a function and moveZheng Bao2021-11-111-13/+15
| | | | | | | | | | | | Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/mediatek/mt8195: fix apusys coding defectsFlora Fu2021-11-111-4/+4
| | | | | | | | | | | | | | | | Use size_t for count variables. Reduce debug log level and fix typo. Fix commit: https://review.coreboot.org/c/coreboot/+/58794 BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: Ic03f71b7a9038edb5877ebd9b6aed5e9bd63c918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59038 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/felwinter: Update typeC EC mux portEric Lai2021-11-111-5/+5
| | | | | | | | | | | | | | | | | | | | We need to put USB setting in mux order. BUG=b:204230406 TEST=Type C mux configuration is correct. Wrong: added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Correct: added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/variants/gimble: Update audio setting for SmartAMPMark Hsieh2021-11-112-2/+3
| | | | | | | | | | | | | Divide dsm_param_file_name into dsm_param_R and dsm_param_L BUG=b:205684021 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59046 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/galtic: update Wifi SAR for convertiblesFrankChu2021-11-111-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | Add wifi sar for galtic/galtic360/galith360 Using convertible mode of SKU ID to load wifi table. Each Project and SKU ID correspond as below galtic (sku id:0x120000) galith (sku id:0x130000) gallop (sku id:0x150000) galtic360 (sku id:0x260000) galith360 (sku id:0x270000) BUG=b:203741126 TEST=emerge-dedede coreboot chromeos-bootimage \ coreboot-private-files-baseboard-dedede verify the SAR table is correct in each project Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* Spell Intel Cooper Lake-SP with a spacePaul Menzel2021-11-113-3/+3
| | | | | | | | | | | | Use the official spelling. [1] [1]: https://ark.intel.com/content/www/us/en/ark/products/codename/189143/products-formerly-cooper-lake.html Change-Id: I7dbd332600caa7c04fc4f6bac53880e832e97bda Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* samsung/lumpy,stumpy: Add get_power_switch()Kyösti Mälkki2021-11-114-8/+22
| | | | | | | | Change-Id: I75c2e86e64943eb241db48482746317ed9ba47af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* samsung/lumpy: Add get_lid_switch()Kyösti Mälkki2021-11-111-2/+6
| | | | | | | | Change-Id: Ib360a6fa00d0ebda4635b96f1b671a66c1ca11c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* google/beltino,jecht: Refactor ChromeOS GPIOsKyösti Mälkki2021-11-114-10/+37
| | | | | | | | Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* samsung/lumpy,stumpy: Refactor ChromeOS GPIOsKyösti Mälkki2021-11-114-10/+45
| | | | | | | | Change-Id: Ic8b189dd82c412aa439694e200d530ae7e71d7e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik2021-11-1115-107/+404
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ChromeOS: Replace with or add <types.h>Kyösti Mälkki2021-11-1164-19/+64
| | | | | | | | | | | | | It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* intel/strago: Fix some CHROMEOS guardsKyösti Mälkki2021-11-112-8/+7
| | | | | | | | | | | | | MAINBOARD_HAS_CHROMEOS always evaluates true for this board. The commentary about get_write_protect_state() was wrong, it's currently only called in ramstage. Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya: Enable thermal control functionality for tpchSumeet Pawnikar2021-11-111-0/+2
| | | | | | | | | | | | | | | Enable DPTF based thermal control functionality for tpch device on brya device. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/cezanne/fsp_m_parameters: add curly braces around else blockFelix Held2021-11-101-2/+2
| | | | | | | | | | | | Since the if block contains multiple statements, it uses curly braces around them, so also add curly braces around the else block even though it only contains one statement. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia8d6b45ec16916ff77078446414de259cffa1475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59070 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/thread: Start stopwatch after printkRaul E Rangel2021-11-101-2/+2
| | | | | | | | | | | | | | | | | | We are currently counting how long it takes to print the waiting message, in addition to the actual time we spent waiting. This results in inflating the measurement by 1.7ms when the serial console is enabled. This CL makes it so the print happens before the stopwatch starts. BUG=b:179699789 TEST=No longer see printk time taken into account on serial console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib48e37c1b2cb462d634141bf767673936aa2dd26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-10104-194/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/cezanne,picasso/include/southbridge: use bitwise or in definesFelix Held2021-11-102-6/+6
| | | | | | | | | | | | | Use bitwise or instead of additions to build bit masks with multiple bits set. TEST=Timeless build results in identical image on amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/spd_tools: Document adding support for a new memory technologyReka Norman2021-11-092-0/+72
| | | | | | | | | | | | | | | | | Add documentation describing how to add support for a new memory technology to spd_tools: - Add a section to the README. - Document the memTech interface in spd_gen.go. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59005 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne,picasso/include/southbridge: fix typo in defineFelix Held2021-11-092-2/+2
| | | | | | | | | | | | In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16 of the misc I2C pad control registers is defined as BiasCrtEn, so rename I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6%Wisley Chen2021-11-093-0/+8
| | | | | | | | | | | | | | | Set RFI Spread Spectrum to 6% for Redrix as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:200886627 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Enable Intel FIVR RFI settingsWisley Chen2021-11-092-0/+42
| | | | | | | | | | | | | | Add RFI UPD settings to mitigate RFI noise issues and exporting these UPDs to override via board devicetree. BUG=b:200886627 TEST=build Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/BReka Norman2021-11-091-2/+2
| | | | | | | | | | | | | | | During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is copied to CSE_RW, so the sizes of these regions need to match. BUG=b:189177538 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* google/trogdor: Update the power on sequence of ps8640xuxinxiong2021-11-092-3/+11
| | | | | | | | | | | | | | | | | For the Qualcomm PBL configuration of GPIO, we need to initial the GPIOs for VDD33# and RST# at the beginning of coreboot. According to the pa8640 latest spec v1.4, update the sequence of VDD33# and PD#. BUG=b:204637643 BRANCH=trogdor TEST=verified the waveform of ps8640 at coreboot phase. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: Ia378aafa49ec462c990501ce48721e330d9648b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58994 Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/metaknight: Probe and enable amplifier operation modeDavid Wu2021-11-091-3/+16
| | | | | | | | | | | | | | | Probe the fw_config for RT1015 speaker amplifier operation mode and enable it accordingly in the device tree. BUG=none BRANCH=dedede TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2de1487b7f4767e9ba6432174c39feeb25f9534c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/bugzzy: Adjust I2C speedSeunghwan Kim2021-11-091-0/+6
| | | | | | | | | | | | | | | | This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns and fall_time_ns values for each port are capured by a scope. BUG=None BRANCH=dedede TEST=built and verified adjusted I2C speed < 400KHz Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/magolor: Enable ELAN touchscreen for magnetoTyler Wang2021-11-091-0/+21
| | | | | | | | | | | | | Add ELAN touchscreen support for magneto. BUG=b:203122673 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/bugzzy: Update charger performance control tableSeunghwan Kim2021-11-091-4/+4
| | | | | | | | | | | | | | | | | Update charger performance control table of DPTF for bugzzy. Since the EC change chromium:197776876 modified maximum charging current to reduce skin temperature, this change adjusts the charging performance table with the modified value. BUG=b:197776876 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/bugzzy: Enable Wifi SARSeunghwan Kim2021-11-091-0/+1
| | | | | | | | | | | | | | BUG=None BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot chromeos-bootimage Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ie967ef7fbc19886c631e634a0b0c3f2cf1e490af Reviewed-on: https://review.coreboot.org/c/coreboot/+/58845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel: generate SSDT instead of using GNVS for SGXMichael Niewöhner2021-11-0910-50/+45
| | | | | | | | | | | GNVS should not be used for values that are static at runtime. Thus, use SSDT for the SGX fields. Change-Id: Icf9f035e0c2b8617eef82fb043293bcb913e3012 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Documentation/security/vboot: Update 4.15 vboot supported boards4.154.15_branchJason Glenesk2021-11-091-34/+44
| | | | | | | | | | | | Update list of boards that support vboot. Change-Id: Id5d4d18202bf85c5ba407efd690eee5cba88a8a7 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58975 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/releases: Update 4.16 target date and cadence informationJason Glenesk2021-11-091-1/+4
| | | | | | | | | | Change-Id: I6c8327a7cf47217d32359b304b21e806c10dcc62 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Documentation/releases: Update 4.15 release notesJason Glenesk2021-11-091-4/+8
| | | | | | | | | | | | Update details for upcoming 4.15 release Change-Id: Ie4d47456cce38e7ec4329f8cb839167017c7e26b Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* emulation/qemu-i440fx,q35: Split chromeos.cKyösti Mälkki2021-11-096-41/+35
| | | | | | | | | | | | | | | | This drops VBOOT_NO_BOARD_SUPPORT. There is little impact of always having recovery_mode_switch() implemented in bootmode.c. A weak write_protect_state() is not necessary as there is no BOOT_DEVICE_SPI_FLASH with the emulation. Call to fill_lb_gpios() is already guarded with CONFIG(CHROMEOS) so the weak implementation would not be referenced. Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/lint/kconfig_lint: Fix off by one error that missed last lineMartin Roth2021-11-091-1/+1
| | | | | | | | | | | | | | This error prevented the last line of the Kconfig tree from being printed or added to the output file. This is a significant problem if you try to use the generated file as the kconfig source, because it changes CONFIG_HAVE_RAMSTAGE from defaulting to yes to defaulting to NO. This causes the build to stop working. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* amd/sata: Remove the weak functionZheng Bao2021-11-091-2/+0
| | | | | | | | | | BUG=b:140165023 Change-Id: I1908f727a7be1e33cbfd273b7261cbd989a414fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* pci_mmio_cfg: Always use pci_s_* functionsNico Huber2021-11-097-65/+30
| | | | | | | | | | | | | | When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* pci_mmio_cfg: Gather everything MMCONF (ECAM) relatedNico Huber2021-11-091-16/+16
| | | | | | | | | | | | | | | To ease code sharing with other MMIO-based configuration mechanisms, move everything MMCONF (more specifically ECAM) related to one spot and guard it. Change-Id: Idda2320c331499dabbee7447f1ad3e81340f2a25 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* pci_mmio_cfg: Move guard around pci_s_* functions to x86Nico Huber2021-11-092-2/+4
| | | | | | | | | | | | | | | | There is no platform in our tree that requires the PCI MMIO ops but doesn't want the pci_s_* definitions. The only case where we include the `pci_mmio_cfg.h` header but don't want the pci_s_* functions to use MMIO is on older x86 platforms, so move the guard there. Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki2021-11-0950-35/+21
| | | | | | | | Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/nvidia,qualcomm: Fix indirect includesKyösti Mälkki2021-11-094-18/+2
| | | | | | | | | | | | Avoid indirect <vc/google/chromeos/chromeos.h> as the files really only need <security/vboot/vboot_common.h>. Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`Michael Niewöhner2021-11-0811-21/+1
| | | | | | | | | | | | | | | | | | | | | Technically, it's not depending on the hardware but on the software (OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A support disabling of the PM Timer, when the respective FADT flag is unset. Thus, drop this guard. For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`. As of this change, new platforms must either implement code for disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such is present. Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
* drivers/intel/fsp2_0: Add preload_fspm and preload_fspsRaul E Rangel2021-11-083-0/+20
| | | | | | | | | | | | | | | | In the non-XIP world, FSP is normally memmapped and then decompressed. The AMD SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X optionRaul E Rangel2021-11-082-0/+16
| | | | | | | | | | | | | | This option will allow setting the FSP alignment in CBFS. BUG=b:179699789 TEST=Boot with and without the option set and verify -a option was passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/{cezanne,picasso}: Stop passing base for fspm.binRaul E Rangel2021-11-082-4/+0
| | | | | | | | | | | | | We no longer need to do this since we relocate at runtime. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 00:54:49 +0000