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* ec/starlabs/merlin: Remove the CMOS Bank 1 entriesSean Rhodes2024-02-151-16/+0
| | | | | | | | | | These entries no longer exist as they are stored in CFR. Change-Id: Ia85855fddc36db76a65490a1d685e1943db28b74 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mainboard/qemu-aarch64: Map entire RAM space as read-write memoryAlper Nebi Yasak2024-02-151-2/+1
| | | | | | | | | | | | | | | | | | | | | Commit 977b8e83cb0a ("mb/emulation/qemu-aarch64: Add MMU support") adds MMU support for ARM64 QEMU VMs, but registers a limited 1GiB region for the DRAM, with a note that ramstage should update it. However on recent versions of QEMU "virt" VMs, accessing RAM outside this registered region results in an exception even if the address is backed by actual RAM. This interferes with RAM detection which catches these exceptions, effectively limiting us to detecting a maximum 1GiB of RAM even if more is available. Register the entire RAM space to MMU instead of just the 1GiB, so that probing RAM addresses can correctly detect how much RAM we have. Change-Id: I3afbd27b91ab37304a29a62506f965ac3cfb1c06 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* util/ifdtool.c: Fix long_options for platformVojtech Vesely2024-02-151-1/+1
| | | | | | | | | | | Platform has argument, but has_arg was mistakenly set to 0. Change-Id: I7d5c31c2b1da544cb73d9e213d463332fcdba7df Signed-off-by: Vojtech Vesely <vojtech.vesely@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80432 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
* mb/lenovo/x230: Disable the USB P8 portAlexei Sorokin2024-02-151-1/+1
| | | | | | | | | | | | | | | | This port is not connected on the X230, X230i, X230t. When X230 support was introduced and pei_data was filled in, this port was disabled, but after commit 3dc12c1e1918 (bd82x6x: Consolidate early native USB init) it has become enabled. Change-Id: I952193798c0894b256b21d9fb3f238074ff5f0f0 Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80468 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop unused soft_reserved_ram_resource macroFelix Held2024-02-141-3/+0
| | | | | | | | | | | | The unused soft_reserved_ram_resource expanded to the non-existent fixed_mem_resource function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b454175c6530e539aa24dffb771368b0aea6da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/dedede/Kconfig.name: Alphabetize board listingMatt DeVillier2024-02-141-54/+54
| | | | | | | | Change-Id: I7230bb8f9883f186c10f41132a2919c3fd99f8c1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/dedede/Kconfig: Alphabetize selections for baseboardsMatt DeVillier2024-02-141-8/+8
| | | | | | | | Change-Id: I245eb8a9961e3e0025c0275f306a4d989b532331 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80491 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/Kconfig: Alphabetize variant board listingsMatt DeVillier2024-02-141-139/+139
| | | | | | | | Change-Id: I2909375d38c37332293bd7928ae33d5bb502694f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80490 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/showdevicetree: drop unmaintained toolFelix Held2024-02-144-159/+0
| | | | | | | | | | | | | This tool doesn't have a makefile, when trying to compile it manually with the given instructions it even fails to compile after fixing the paths in the given command, and it references the non-existing PCI_BUS_SEGN_BITS Kconfig symbol, so just drop this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79934 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drv/gfx/generic: Add Intel ACPI Backlight funcs for LCD devicesMatt DeVillier2024-02-141-0/+36
| | | | | | | | | | | | | | | | Normally this would be done by the Intel GMA driver, but we can't have two copies of the _DOD method, so generate the LCD backlight controls here to allow use of this driver instead of the default GMA panel definition. TEST=build/boot Win11 on google/byra (redrix), ensure ACPI brightness controls functional. Change-Id: Ic8fbaf7550405f8c6f36012c8efadb8c36b968c2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80061 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Add VBTs and select INTEL_GMA_HAVE_VBTMatt DeVillier2024-02-1420-0/+19
| | | | | | | | | | Vbt data files extracted from dedede recovery image 120.0.6099.272. Change-Id: I28485d501e519cdaa06c55c20eba07190c5c6b6f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/starlabs/starbook/kbl: Remove tcc_offset entrySean Rhodes2024-02-141-3/+0
| | | | | | | | | | | The TCC offset is configured in devtree.c, so remove it from the devicetree. Change-Id: I044a68854cc142b057cf31b4e2456d2ad1d0dd3a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/starlabs/merlin: Remove the call to pc_keyboard_initSean Rhodes2024-02-141-2/+0
| | | | | | | | | | As DRIVERS_PS2_KEYBOARD isn't set, this function is not doing anything. Change-Id: Ie8842a32fca56f330a0f044cf96112dc5cae6546 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Documentation/vboot: Update vboot supported boards listMatt DeVillier2024-02-141-10/+12
| | | | | | | | | | Auto-generated by util/vboot_list/vboot_list.sh. Change-Id: I35dc51915c8468543c981e1b046e4ecf8d5b4bbf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* tree; Remove unused <lib.h>Elyes Haouas2024-02-148-8/+0
| | | | | | | | | Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80433 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/x230: introduce EDP variantAlexander Couzens2024-02-145-6/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a modification for the x230 which uses the 2nd DP from the dock as the integrated panel's connection, which allows using a custom eDP panel instead of the stock LVDS display. There are several adapter boards present on the market and all of them use the same method of enabling the custom eDP panel. To make this work with coreboot, the internal LVDS connector should be disabled in libgfxinit. Additionally, VBT has been modified to keep brightness controls functional on the adapter boards that use LVDS for the job. The modifications done to the VBT are: - Remove the LVDS port entry. - Move the DP-3 (which is the 2nd DP on the dock) entry to the first position on the list. - Set the DP-3 as internally connected. This has been reported to work with the following panels: - LP125WF2-SPB4 (1920*1080, 12.5") - LQ125T1JW02 (2560*1440, 12.5") - LQ133M1JW21 (1920*1080, 13.3") - LTN133HL10-201 (1920*1080, 13.3") - B133HAN04.6 (1920*1080, 13.3") - B133QAN02.0 (2560*1600, 13.3") Other eDP panels not on this list should work as well. Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mainboard: Enforce usage of AZALIA_ARRAY_SIZESNicholas Sudsgaard2024-02-1311-22/+11
| | | | | | | | | | | This is the de facto method and should be enforced to keep things consistent. Change-Id: I7eee77f7fd49bc38e27cb0e6be0a4a6555098cc7 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/clevo/tgl-u: Use enum for AZALIA_PIN_CFG misc fieldNicholas Chin2024-02-131-11/+11
| | | | | | | | | | | | | Use the new JACK_PRESENCE_DETECT and NO_JACK_PRESENCE_DETECT enums instead of raw values in the misc field of AZALIA_PIN_CFG. TEST: Timeless build for clevo/tgl-u did not change Change-Id: Ic3f4128ecbf89ddce3b6e705ebef76da343a433c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* include/device/azalia_device.h: Add enum for misc fieldNicholas Chin2024-02-131-2/+7
| | | | | | | | | | | | | | | | The HDA specification defines bits 11:8 of the Configuration Default register as a miscellaneous field for other jack information. Only bit 8 has a standard meaning, and indicates that the jack does not have presence detect capability. Add an enum for use in the AZALIA_PIN_DESC macro to indicate this field. Note that many vendor firmwares set bits 11:9 to non zero values despite them being reserved in the specification, and their meaning in these cases is not well known. Change-Id: I70cbfca8541828a1e0c7280887060c04e4c71721 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/*: Replace use of gfx/generic addr field with display typeMatt DeVillier2024-02-1328-32/+32
| | | | | | | | | | | | | | | Eliminates the use of a magic number, and the resulting DID entry in the _DOD method is the same. TEST=build/boot google/drallion, dump SSDT and verify DID entry is unchanged. Change-Id: Ic929cf7ec6849ba398653226bbe46d27b4e3fa81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* drivers/gfx/generic: Add display type fieldMatt DeVillier2024-02-132-2/+24
| | | | | | | | | | | | | | | | | | | | Add an enum for the Display Type, which if set, can be used to generate the Device ID value dynamically when the addr field is not set. This will allow devicetree entries to specify the display type instead of a hex value for the address which requires referencing the ACPI spec to decode. For an internal panel connected to the first port on the graphics chip, currently an addr value of 0x80010400 is specified. Replacing the 'addr' field with the 'type' field and setting it to 'panel' will generate the same DID value. Change-Id: Id0294a14606b410a13fa22eeb240df9e409a7ca3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/brox: Set display output type for eDP panelMatt DeVillier2024-02-131-0/+1
| | | | | | | | | | | | | Set the display type for the LCD panel configured via the gfx/generic driver. This will ensure the correct DID/device address are generated in the SSDT. Change-Id: If63374329ed5eb4330517ca1bf2ba1ada24fa54a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80244 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: Use name 'LCD0' for internal panel outputMatt DeVillier2024-02-131-1/+1
| | | | | | | | | | | | | The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. Change-Id: Id52f7c0e542423ba08eeed89bf9b171e540e10e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/rex: Use name 'LCD0' for internal panel outputMatt DeVillier2024-02-132-2/+2
| | | | | | | | | | | | | The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. Change-Id: Id93cfea93edfefc8237b53214734531b811b36e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80202 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Set display output type for eDP panelMatt DeVillier2024-02-132-0/+2
| | | | | | | | | | | | | Set the display type for the LCD panel configured via the gfx/generic driver. This will ensure the correct DID/device address are generated in the SSDT. Change-Id: I8f390c58710c91bf77555f664e8f89f08ca59b30 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/hatch/var/jinlon: Ensure LCD backlight controls generatedMatt DeVillier2024-02-132-1/+9
| | | | | | | | | | | | | | | | | | Jinlon disables the eps device if no privacy screen is present, so add a second generic gfx device 'no_eps' to handle that case, so that ACPI backlight controls are generated either way. Add logic to ensure only one of the two devices is active. TEST=build/boot Win11 on google/hatch (jinlon), ensure LCD backlight controls present and functional on device both with and without a privacy screen. Change-Id: Icf20de97d26c8be76c84e87d5dc6ed1a4b6dbfbc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80178 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/var/jinlon: Use name 'LCD0' for internal panel outputMatt DeVillier2024-02-131-1/+1
| | | | | | | | | | | | | | | | The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. TEST=build/boot Win11 on google/hatch (jinlon), verify LCD brightness controls are functional. Change-Id: I4204a518876bed38584260f7566d4d6c9aaa042f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80177 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/*: Use name 'LCD0' for internal panel outputMatt DeVillier2024-02-1325-29/+29
| | | | | | | | | | | | | | | | | | The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. TEST=build/boot Win11 on google/brya (redrix), verify brightness controls are functional. Change-Id: I389553b2ddc5b09d165229e2d8066cacf852b82c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80174 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Won Chung <wonchung@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/drallion: Drop GMA default panelMatt DeVillier2024-02-131-1/+0
| | | | | | | | | | | Redundant when generic gfx driver is used Change-Id: I8ed1eede05f531f4c76e7fa168c2b92fae7e45cb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/drallion: Use name 'LCD0' for internal panel outputMatt DeVillier2024-02-131-1/+1
| | | | | | | | | | | | | | | | The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. TEST=build/boot Win11 on google/drallion, verify brightness controls are functional. Change-Id: I6fbdd0c5606ec8f2c497e85bf46d388957f15fa5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80175 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/puff: Hide LSPCON device from WindowsMatt DeVillier2024-02-139-18/+18
| | | | | | | | | | | | | | | | | | | Puff-based Chromeboxes use a LSPCON for HDMI 2.0 output, but no driver exists or is needed for Windows. Use the devicetree hidden keyword to set the ACPI status to hidden for these devices, to prevent unknown devices from being listed in Windows Device Manager. TEST=build/boot Win11 on google/wyvern, verify no unknown devices in Windows Device Manager for either LSPCON device. Change-Id: Ib646e01a337b8d7baf20a886c49a8cb64d6408f3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78040 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/volteer/drobit: Add a board-specific VBT fileMatt DeVillier2024-02-132-1/+2
| | | | | | | | | | | | | | | | | Add a board-specific VBT file compatible with the latest FSP release (requires VBT version 250). TODO: Update all other volteer VBTs to v250 from v240. TEST=build/boot google/volteer (drobit) with edk2 payload Change-Id: Ie25a77be5204dfc8b888082492a285973843037c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80183 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/alderlake: Leverage IA common code for range calculationsSubrata Banik2024-02-132-126/+4
| | | | | | | | | | | | | | | | Improves code maintainability and potentially reduces redundancy by using the IA common implementation. Additionally, drop the unused macros from SoC local. TEST=Build and boot successful on google/marasov. Change-Id: I290fea99f04cfc9f18e5f1435ed07de42995869f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80403 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Leverage IA common code for range calculationsSubrata Banik2024-02-132-126/+4
| | | | | | | | | | | | | | | | | Improves code maintainability and potentially reduces redundancy by using the IA common implementation. Additionally, drop the unused macros from SoC local. TEST=Build and boot successful on google/screebo. Change-Id: Ie0baae1d3b0093389649dee3531902c5e86c02fe Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80404 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/cmn/sa: Add APIs into System Agent (SA) common codeSubrata Banik2024-02-133-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit streamlines code and strengthens common code robustness by moving the following SoC-layer functions to the common layer: - sa_get_mmcfg_size: Retrieves the MMIO (Memory-Mapped I/O) configuration space size by reading offset 0x60 of the PCI Host Bridge (D0:F0). - sa_get_dsm_size: Calculates the size of the DSM (Device Stolen Memory) by reading offset 0x50 of the PCI Host Bridge (D0:F0) to determine pre-allocated memory for the IGD (Integrated Graphics Device). - sa_get_gsm_size: Calculates the size of the GSM (Graphics Stolen Memory) by reading offset 0x52 of the PCI Host Bridge (D0:F0). - sa_get_dpr_size: Determines the size of the DMA Protection Range (DPR) by reading offset 0x5C of the PCI Host Bridge (D0:F0). TEST= Build and boot successful on google/screebo. Change-Id: Ic00e001563ec6f0d737a445964c716b45db43327 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/asus/p8z77-m/hda_verb.c: Use existing defines for NC pinsKeith Hui2024-02-121-6/+6
| | | | | | | | | | | | | | Goal is to use existing defines for all pins to make the file self-documenting, but it would make lines too long, so I'll just start with the NC pins. TEST=Timeless binary did not change. Change-Id: I6da02d7bc4c87cc8477d687b238e6e6c9aec62cd Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79733 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Use gpp_clk_setup_common functionVarshit Pandya2024-02-123-53/+2
| | | | | | | | | | In follow up to CB:80285 use gpp_clk_setup_common for picasso as well. Change-Id: I68d498d08d5975037086c84ff2f7fdb265ee84d9 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80414 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_configVarshit Pandya2024-02-123-6/+7
| | | | | | | | | | | | | | | This function turns off gpp_clk for the devices which are disabled, and adds the code to fix up the clock configuration depending on dxio descriptors. Also this brings picasso in line with cezanne, mendocino and phoenix. This also prepares picasso to use the common function gpp_clk_setup_common. Change-Id: Ice2e3a5a78359da9a438434c7d4aa1eca878d396 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80413 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* vc/amd/fsp/picasso: Bring picasso inline with other AMD SoCVarshit Pandya2024-02-121-2/+3
| | | | | | | | | | | | | In preparation to using gpp_clk_setup_common for picasso, bring enum defined in picasso more in line with other AMD SoC. Change-Id: I9753acdff15921c84516ec873c925f36afdd2aa3 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80412 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* ec/lenovo/h8/acpi: Support pulsing LEDLOGO on Haswell ThinkPadsEvgeny Sorokin2024-02-123-0/+21
| | | | | | | | | | | | | | | | | | | | | | | The name LEDLOGO comes from schematics. It's the red indicator, embedded in the dot of the 'i' of the ThinkPad logo on laptop's lid. In vendor firmware, this led starts fading in-and-out, or, in other words, pulsing, when laptop is put to S3. It helps to determine whether the laptop is in S3 just by taking a look at the logo. As of now, coreboot doesn't do anything with this particular indicator, it's always in enabled (on) state, which is not very convenient. This patch fixes it. Tested on T440p. Change-Id: I85fb69c8c1bed8635a1b31e9b8385c7036bb46dd Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80437 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/intelmetool: Add Intel Union Point supportNicholas Sudsgaard2024-02-121-0/+22
| | | | | | | | | | The device IDs were taken from the 200 series datasheet (page 24). Change-Id: I34b5cb61dd7b561778cc8506858cd436e6f04f9a Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80419 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* crossgcc: Add buildgcc support for Apple M1/M2 devicesStefan Reinauer2024-02-121-1/+4
| | | | | | | | | | | | | | GMP and IASL don't compile with the default compiler and linker flags: - GMP's check for the MacOS architecture hard coded x86_64 but it also needs to know about arm64. - iasl does some trickery on pointer alignment to save space(?), so we need to tell clang about it. Change-Id: If4cca9d3e55051a6121d992e5320bee1df17af9f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80435 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/sa: Refactor SA common codeSubrata Banik2024-02-126-41/+32
| | | | | | | | | | | | | | | | | | Leverages common SA header definitions for Host Bridge registers. Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity. Additionally, made some minor code alignment corrections while adding newer macros in the header file. TEST= Build and boot successful on google/screebo. Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
* drivers/uart/sifive.c: Fix divisor calculationMaximilian Brune2024-02-101-3/+10
| | | | | | | | | | | | | | | The divisor is calculated using the following formula: div = (frequency / baudrate) - 1; The current implementation however essentially calculates: div = (frequency / baudrate); Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I8a0898ce9016a70c0f91dc8a99fc1cf9e46d20c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79951 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* arch/riscv/boot.c: Comment OpenSBI Supervisor mode switchMaximilian Brune2024-02-101-2/+4
| | | | | | | | | | | | | | It simply adds a comment to indicate to the reader that the RISCV_PAYLOAD_MODE_S parameter causes OpenSBI to switch to Supervisor mode. Otherwise it could be interpreted that coreboot switches to Supervisor mode before starting OpenSBI (which is not the case) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ib62be0c2ff59361200df4c65f9aca5f7456a0ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/79949 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
* soc/amd: Factor out gpp_clk_setup functionVarshit Pandya2024-02-1013-160/+80
| | | | | | | | | | | | | | | | gpp_clk_setup code in most AMD SoC is similar and it can moved to common code. The only thing which is SoC dependent in this function is the SoC config, hence keep it in SoC code and move everything else in new gpp_clk_setup_common function which is in soc/amd/common. Picasso and Glinda don't have pcie_gpp_dxio_update_clk_req_config fixup function so they are addressed in later patches. Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80285 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: Initialize TCHSCR_RST_L to 0Shelley Chen2024-02-091-0/+4
| | | | | | | | | | | | | | | | | | TCHSCR_RST_L signal was originally being configured to 1 in gpio.c but this was causing some leakage. Configuring it to 0 initially in romstage fixes this. Also, make sure that EN_PP3300_TCHSCR is initialized in romstage as well. BUG=b:322249892 BRANCH=None TEST=Make brox boots and touchscreen is still working Change-Id: I5bf1901a3a40a38237b950abcb758f96aebcc1cf Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80300 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpi: Pass struct device to acpi_create_srat_gia_pciPatrick Rudolph2024-02-093-16/+15
| | | | | | | | | | | | | | Instead of S:B:D:F numbers pass the struct device to acpi_create_srat_gia_pci and let it extract the information needed. This also adds support for PCI multi segment groups. Change-Id: Iafe32e98f0c85f14347695ccaa0225e43fad99e7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80258 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp/numa: Store pointer to devicePatrick Rudolph2024-02-095-8/+9
| | | | | | | | | | | Instead of a BDF number store a pointer to the device itself. Change-Id: I3fef93c5e54c8af792102bcd25364c43b554a5f0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/nissa: Skip GPP_F15 GPIO locking to avoid IRQ stormWeimin Wu2024-02-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an existing issue for nissa where wake up from RTC wake is not working during suspend_stress_test. The phenomenon of the issue is that after pulling out the stylus, can see an interrupt storm occurs, checking through: "cat /proc/interrupts | grep acpi". When the counter of interrupt is greater than a certain value, "Disabling IRQ #9" will occur, so RTC wake is not working. Reference: https://review.coreboot.org/c/coreboot/+/65086 This patch skips the locking for GPP_F15 to allow kernel to configure it later. The interrupt storm of acpi disappears. BUG=b:321348117 TEST=1. cat /proc/interrupts | grep acpi there isn't interrupt storm of acpi when pulling out stylus. 2. The stylus tools panel will pop up when pulling out it. 3. Inserts stylus can wakeup DUT after powerd_dbus_suspend. 4. Passed: suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20 Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80316 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-28 17:59:40 +0000