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* Documentation: Fix spelling errorsMartin Roth2021-10-051-1/+1
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/mipi: Move to drivers/mipiJulius Werner2021-08-261-1/+1
| | | | | | | | | | | | | | Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Documentation/drivers/dptf: Add oem variables supportSumeet Pawnikar2021-07-081-0/+16
| | | | | | | | | | | | | | Add oem variables information with usage example. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: I45db17f6ee3328da28f985c6854d65a430c9c61b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Documentation: Fix toctree and remove dead linksPatrick Rudolph2021-01-121-0/+2
| | | | | | | | Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph2020-10-222-0/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie2020-10-191-0/+40
| | | | | | | | | | | | | | | | The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add documentation for drivers/intel/dptf chip driverTim Wawrzynczak2020-07-181-0/+313
| | | | | | | | | Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8915ead08a89dcf95fd92983eca5f85b82916dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/43533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* smmstore: Verify userspace-provided pointer to protect SMMPatrick Rudolph2020-06-171-1/+12
| | | | | | | | | | | | | | Use the introduced functions and verify pointers in the SMMSTORE. Make sure to not overwrite or leak data from SMM and update the documentation as well. Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add info about SoundWire coreboot implementationDuncan Laurie2020-05-222-0/+497
| | | | | | | | | | | | | | | This change adds a document about the SoundWire implementation in coreboot with details adding new controllers and codecs and connecting them in the mainboard devicetree. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ibc04442e22acfc03ff86c49c8a7a215ceefc24c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40892 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Spell vboot all lowercasePatrick Rudolph2020-04-281-1/+1
| | | | | | | | | | | Update all occurrences of vboot and spell it lowercase. Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation: Add SMMSTORE documentationArthur Heymans2019-11-292-0/+124
| | | | | | | | | | This documents the smmstore API. Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation/drivers: Fix typo in index.mdTim Wawrzynczak2019-08-021-1/+1
| | | | | | | | Change-Id: Ibf8f37d1e1223c5481cf1a40f08d4113bd80ed41 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* drivers/ipmi: Add chip opsPatrick Rudolph2019-06-212-0/+54
* Add chips ops for IPMI KCS. * Get IPMI version over KCS. * Generates ACPI SPMI table for IPMI KCS. * Generates SMBIOS type 38 for IPMI KCS. * Generates ACPI SPMI device for IPMI KCS on LPC device. * Add documentation To use this driver on BMC that support KCS on I/O: 1. Add an entry to the devicetree.cb: chip drivers/ipmi device pnp ca2.0 on end # IPMI KCS end 2. Select IPMI_KCS in Kconfig. 3. (Optional) enable LPC I/O decode for the given address. Tested on Wedge100s. Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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