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* Documentation: Add wake source info to device tree documentationRaul E Rangel2022-12-131-22/+92
| | | | | | | | | | | | | | | | | | | | The device tree documentation was promoting using a GPIO wake event and a GPE wake event. We should only ever have one. This wasn't actually causing a problem because the wake bit was set on the `irq` property, but the IO-APIC can't actually wake the system, so it was a no-op. This change fixes up the markdown so it's formatted correctly, and also adds a section explaining what the different wake configurations are. BUG=b:243700486 TEST=mdformat Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67385 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/drivers: Update section on touchscreen runtime detectionMatt DeVillier2022-11-071-3/+4
| | | | | | | | | | | | Update section now that google/skyrim and google/guybrush implement power sequencing and touchscreen runtime detection. Change-Id: Ida63bebf18575d6856edfc65965ff82a4072df87 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Documentation/drivers/cbfs_smbios.md: Describe CBFS serial numberMichał Żygowski2022-10-171-0/+78
| | | | | | | | Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6f0963417c7c580f903922ac88c95569c8782bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* drivers/generic/cbfs-uuid: Add driver to include UUID from CBFSMichał Żygowski2022-10-112-0/+66
| | | | | | | | | | | | | | | When system_uuid CBFS file is present and contains the UUID in a string format, the driver will parse it and convert to binary format to populate the SMBIOS type 1 UUID field. TEST=Add UUID file and boot MSI PRO Z690-A DDR4 WIFI and check with dmidecode if the UUID is populated correctly. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I22f22f4e8742716283d2fcaba4894c06cef3a4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/64639 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/ipmi: prepare for adding more interfacesSergii Dmytruk2022-10-021-0/+9
| | | | | | | | | | | | De-duplicate common initialization code (self-test and device identification) and put it in a new ipmi_if.c unit, which is supposed to work with any underlying IPMI interface. Change-Id: Ia99da6fb63adb7bf556d3d6f7964b34831be8a2f Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* Documentation/drivers: Add section for i2c detect featureMatt DeVillier2022-09-261-2/+30
| | | | | | | | | | | Add a section explaining how the detect feature works and when it should be used. Change-Id: Ife5178d4565e76d0ff436c835c9c47525015c3ed Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Documentation/drivers: ensure pages have only one top-level headingMatt DeVillier2022-09-232-16/+16
| | | | | | | | | | | | Having multiple top-level headings breaks sphinx-doc's TOC generation, so adjust driver sub-pages to only have a single one. Adjust other headings as needed to preseve page layout. Change-Id: Ib8a334c73daefffafa779957cc8e47a9cad4a202 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Documentation: split devicetree driver hookup into separate pageMatt DeVillier2022-09-232-0/+214
| | | | | | | | | | | | | Move the devicetree driver example into a separate page under the drivers category, and link to it from both the devicetree page and the drivers index page. This makes more sense from a grouping perspective and makes the info easier to find. Change-Id: Ic3ca80b93a0020737c7ccb5313a0877172022e1a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Documentation: alphabetize driver pages/linksMatt DeVillier2022-09-231-1/+1
| | | | | | | | Change-Id: Ib25ad5fdedc9b6c46245b823caaae5705af2bfb8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* payloads/tianocore: Rename TianoCore to edk2Sean Rhodes2022-08-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | coreboot uses TianoCore interchangeably with EDK II, and whilst the meaning is generally clear, it's not the payload it uses. EDK II is commonly written as edk2. coreboot builds edk2 directly from the edk2 repository. Whilst it can build some components from edk2-platforms, the target is still edk2. [1] tianocore.org - "Welcome to TianoCore, the community supporting" [2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and UEFI Platform Initialization (PI) specifications." Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Fix spelling errorsMartin Roth2021-10-051-1/+1
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/mipi: Move to drivers/mipiJulius Werner2021-08-261-1/+1
| | | | | | | | | | | | | | Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Documentation/drivers/dptf: Add oem variables supportSumeet Pawnikar2021-07-081-0/+16
| | | | | | | | | | | | | | Add oem variables information with usage example. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: I45db17f6ee3328da28f985c6854d65a430c9c61b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Documentation: Fix toctree and remove dead linksPatrick Rudolph2021-01-121-0/+2
| | | | | | | | Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph2020-10-222-0/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie2020-10-191-0/+40
| | | | | | | | | | | | | | | | The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add documentation for drivers/intel/dptf chip driverTim Wawrzynczak2020-07-181-0/+313
| | | | | | | | | Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8915ead08a89dcf95fd92983eca5f85b82916dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/43533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* smmstore: Verify userspace-provided pointer to protect SMMPatrick Rudolph2020-06-171-1/+12
| | | | | | | | | | | | | | Use the introduced functions and verify pointers in the SMMSTORE. Make sure to not overwrite or leak data from SMM and update the documentation as well. Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add info about SoundWire coreboot implementationDuncan Laurie2020-05-222-0/+497
| | | | | | | | | | | | | | | This change adds a document about the SoundWire implementation in coreboot with details adding new controllers and codecs and connecting them in the mainboard devicetree. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ibc04442e22acfc03ff86c49c8a7a215ceefc24c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40892 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Spell vboot all lowercasePatrick Rudolph2020-04-281-1/+1
| | | | | | | | | | | Update all occurrences of vboot and spell it lowercase. Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation: Add SMMSTORE documentationArthur Heymans2019-11-292-0/+124
| | | | | | | | | | This documents the smmstore API. Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation/drivers: Fix typo in index.mdTim Wawrzynczak2019-08-021-1/+1
| | | | | | | | Change-Id: Ibf8f37d1e1223c5481cf1a40f08d4113bd80ed41 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* drivers/ipmi: Add chip opsPatrick Rudolph2019-06-212-0/+54
* Add chips ops for IPMI KCS. * Get IPMI version over KCS. * Generates ACPI SPMI table for IPMI KCS. * Generates SMBIOS type 38 for IPMI KCS. * Generates ACPI SPMI device for IPMI KCS on LPC device. * Add documentation To use this driver on BMC that support KCS on I/O: 1. Add an entry to the devicetree.cb: chip drivers/ipmi device pnp ca2.0 on end # IPMI KCS end 2. Select IPMI_KCS in Kconfig. 3. (Optional) enable LPC I/O decode for the given address. Tested on Wedge100s. Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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