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x86
Commit message (
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Author
Age
Files
Lines
*
Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware
Corey Osgood
2009-04-14
2
-19
/
+22
*
last kontron commit.
Ronald G. Minnich
2009-03-11
2
-38
/
+204
*
This is working up to the ljmpl to protected mode. It has all the
Ronald G. Minnich
2009-03-05
1
-2
/
+26
*
Again, this probably won't work but I want to make the code visible so
Ronald G. Minnich
2009-02-24
2
-5
/
+6
*
This is a trivial commit and I want to get other people to look at the code.
Ronald G. Minnich
2009-02-21
2
-11
/
+13
*
This patch extends core2 smp support to v3. It is an
Ronald G. Minnich
2009-02-21
3
-6
/
+642
*
The initram build allows you to -fcombine the source. But if you put a
Ronald G. Minnich
2009-02-19
1
-2
/
+11
*
Add this file from v2. Not build tested, just want to get it in.
Ronald G. Minnich
2009-02-18
1
-0
/
+75
*
Improve the setup of MTRRs in stage1 to handle alignment and power of
Marc Jones
2009-02-15
2
-44
/
+159
*
This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Myles Watson
2009-02-12
2
-5
/
+5
*
Add AP detection to stage0 to prevent APs from re-initializing mainboard setup
Marc Jones
2009-02-10
6
-44
/
+64
*
Setup the MTRRs in stage1 so that memory and cache are available throughout
Marc Jones
2009-02-10
3
-49
/
+162
*
Coreboot uses the compiler option -mregparm=3 which causes variables to
Marc Jones
2009-02-10
1
-1
/
+1
*
Remove unused pciconf.h header with constants that everyone uses by value ins...
Mart Raudsepp
2009-01-08
3
-3
/
+0
*
This patch removes the offset_pciio since there is never an offset_pciio an
Myles Watson
2009-01-05
1
-8
/
+6
*
Fix breakage of k8 targets caused by r1085. Thanks to Myles Watson for
Corey Osgood
2008-12-30
2
-4
/
+4
*
This patch fixes a few small problems and gets cn700 to read from an IDE
Corey Osgood
2008-12-23
1
-5
/
+5
*
Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2.
Ronald G. Minnich
2008-12-23
3
-1
/
+464
*
This is an emergency fix for the kontron. This fix now allows us to boot to
Ronald G. Minnich
2008-12-23
1
-1
/
+1
*
Move OPTION_TABLE to a menu config option, and default it to enabled. This al...
Corey Osgood
2008-12-18
2
-8
/
+1
*
Make C7/CN700 boot to memtest86, and pass that test. Booting is very slow, ~1...
Corey Osgood
2008-12-17
2
-0
/
+253
*
Subject: [PATCH 4/5] integration of biosemu (aka YABEL) into coreboot
Myles Watson
2008-12-16
1
-0
/
+6
*
early_mtrr_init() nukes all MTRRs including those which we use for CAR.
Carl-Daniel Hailfinger
2008-12-10
1
-0
/
+6
*
Add support for creating an smm top-level object.
Ronald G. Minnich
2008-12-06
2
-2
/
+14
*
Document unexpected clobbering of stage0 code.
Carl-Daniel Hailfinger
2008-12-03
1
-0
/
+1
*
Fix a missing dependency on arch/x86/stage0_common.S (that's an included
Carl-Daniel Hailfinger
2008-12-03
1
-1
/
+1
*
back out until this issue is really fixed.
Stefan Reinauer
2008-11-26
1
-14
/
+1
*
Experimental backout of the critical code parts in r1057 as requested
Carl-Daniel Hailfinger
2008-11-26
2
-1
/
+4
*
The Core2Duo CAR code did set up the stack incorrectly. In combination
Carl-Daniel Hailfinger
2008-11-25
2
-5
/
+15
*
hack to make v3 rom access a lot faster.
Stefan Reinauer
2008-11-25
2
-1
/
+4
*
get into ram init on kontron board.
Stefan Reinauer
2008-11-25
1
-0
/
+3
*
Not a single file is being rebuilt in v3 if build.h changes. That means
Carl-Daniel Hailfinger
2008-11-16
2
-0
/
+6
*
This patch makes it so serengeti builds again.
Myles Watson
2008-11-14
1
-2
/
+1
*
Add core2 stage1.c dependency
Ronald G. Minnich
2008-11-14
3
-1
/
+102
*
Kill v2 leftovers.
Carl-Daniel Hailfinger
2008-11-13
1
-2
/
+0
*
We are woefully unaware about how much stack v3 really uses.
Carl-Daniel Hailfinger
2008-11-13
2
-0
/
+46
*
The VIA C7 CAR disable code in v3 had a nasty bug which caused the
Carl-Daniel Hailfinger
2008-11-13
1
-12
/
+5
*
I'm committing often as I don't want people to run over each other (and I am ...
Ronald G. Minnich
2008-11-12
1
-8
/
+7
*
initial intel core car code.
Stefan Reinauer
2008-11-12
2
-0
/
+195
*
Filling in core 2 support.
Ronald G. Minnich
2008-11-12
1
-1
/
+13
*
initram is linked with very special options to ld. It is not immediately
Carl-Daniel Hailfinger
2008-11-08
1
-0
/
+2
*
This patch removes code related to PCI type 2 configuration cycles (gone as of
Myles Watson
2008-11-05
1
-16
/
+7
*
Update K8 FID/VID setup to match coreboot v2. Add support for 100MHz FIDs
Marc Jones
2008-11-04
1
-65
/
+148
*
Once we touch the MTRRs in VIA disable_car(), the CPU resets. Since
Carl-Daniel Hailfinger
2008-11-02
2
-2
/
+12
*
Get via to use standard mtrr init functions. Start to document them.
Ronald G. Minnich
2008-11-01
2
-15
/
+4
*
no PIRQ table
Ronald G. Minnich
2008-10-31
1
-1
/
+1
*
This is the beginning of support for saving base registers that already have a v
Ronald G. Minnich
2008-10-31
1
-1
/
+1
*
This patch clears up a few warnings in stage1 code. It removes an unused var...
Myles Watson
2008-10-29
1
-3
/
+2
*
Trivial fixes of printk \r\n and white space.
Myles Watson
2008-10-28
1
-93
/
+93
*
Fix a bunch of Doxygen warnings in v3 (trivial).
Uwe Hermann
2008-10-23
3
-5
/
+6
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